C161V Datasheet, PDF (18/43 Pages) Siemens Semiconductor Group – 16-Bit CMOS Single-Chip Microcontroller

1996 Intermediate Version
C161
In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture
registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The
contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins
(TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or
by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to
alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM
signal, this signal can be constantly generated without software intervention.
Note: The C161V has no external connection for GPT1, ie. the related functions are not available.
Figure 6
Block Diagram of GPT2
With its maximum resolution of 250 ns (@ 16 MHz), the GPT2 module provides precise event
control and time measurement. It includes two timers (T5, T6) and a capture/reload register
(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via
a programmable prescaler. The count direction (up/down) for each timer is programmable by
software. Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6,
which changes its state on each timer overflow/underflow.
The state of this latch may be used to clock timer T5. The overflows/underflows of timer T6 can
cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer
T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may
optionally be cleared after the capture procedure. This allows absolute time differences to be
measured or pulse multiplication to be performed without software overhead.
Note: The GPT2 module is only available on the C161O.
Semiconductor Group
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