TLE4470 Datasheet, PDF (14/22 Pages) Siemens Semiconductor Group – Dual Low-Drop Voltage Regulator

TLE 4470
Input, Output
The input capacitor C_I is necessary for compensating line influences. Using a resistor of
approx. 1 Ω in series with C_I, the LC circuit of input inductivity and input capacitance can
be damped. To stabilize the regulation circuits of the stand-by and main regulator, output
capacitors C_Q1 and C_Q2 are necessary. Stability is guaranteed at values C_Q1 ≥ 6 µF &
C_Q2 ≥ 10 µF, both with an ESR ≤ 10 Ω within the operating temperature range.
For the TLE 4470 G (P-DSO-20-6) the output voltage V_Q2 of the main regulator can be
adjusted to 5 V ≤ V_Q2rated ≤ 20 V by connecting an external voltage divider to the voltage
adjust pin VA. For V_Q2 = 5 V the voltage adjust pin has to be connected directly to the
main output.
For calculating V_Q or R₁ & R₂ respectively the following equations can be used:
V_Q = V_ref × (R₁ + R₂) / R₂
or
R₁ = R × (V_Q / V_ref)
R₂ = R × R₁ / (R₁ – R)
Definitions: R = R₁ // R₂ ; R ≈ 100 kΩ
V_ref = Output voltage of stand by regulator, typical 5 V
Disable
The main regulator of the TLE 4470 can be switched OFF by a voltage of 2.3 V at pin
DIS. Reducing this voltage below 1.4 V will switch ON the main regulator again.
Reset Timing
The power-on reset delay time is defined by the charging time of an external capacitor
C_d which can be calculated as follows:
C_d = (∆t_d × I_d) / ∆V
Definitions: C_d = delay capacitor
∆t_d = delay time
I_d = charge current, typical 5 µA
∆V = V_dt, typical 1.8 V
V_dt = upper delay switching threshold at C_d for reset delay time
The reset reaction time t_rr is the time it takes the voltage regulator to set the reset out
LOW after the output voltage has dropped below the reset threshold. It is typically 2 µs
for delay capacitor of 100 nF. For other values for C_d the reaction time can be estimated
using the following equation:
t_rr ≈ 20 s/F × C_d
Semiconductor Group
14
1998-11-01