SLE4428 Datasheet, PDF (13/17 Pages) Siemens Semiconductor Group – ICs for Chip Cards

SLE 4418
SLE 4428
4
Security Features SLE 4428
Extra Operation for User Identification (Fig. 9)
Without a PSC entry only reading is possible. The contents of the PSC addresses cannot be read
out. If reading is attempted, "00" will appear. The verification procedure of the chip must be
performed in the following sequence (Table 1):
– write one not written error-counter bit, address "1021",
– enter first PSC-code byte, address "1022",
– enter second PSC-code byte, address "1023",
– after correct input the error counter can be erased.
After the PSC verification, I/O goes from "1" to "0". It is switched back to “1” by RST transition “0”
to “1”. The error counter is not automatically erased.
Writing Error Counter
Before PSC entry only writing of the error counter is possible. The number of erased bits of the error
counter determines the number of possible attempts (max. 8). After successful access the error
counter should be erased before disconnecting the supply voltage in order to reactivate the
8 attempts. Each error when entering the PSC requires the writing of a new counter bit.
Entry of PSC
The least-significant PSC byte beginning with the least significant bit must be entered first and then
the most-significant one. If the internal data comparison proves correct, the EEPROM is enabled for
erasing and writing as long as the operating voltage is applied. After enabling, the PSC may be
altered as wished, except the corresponding protect bits are "0".
Condition when supplied
SLE 4428 is only supplied by the producer with a 2-byte PSC (transport code) which is agreed with
the customer.
Table 1
Control Words for Command Entry, User Identification
Byte 1
Byte 2 Byte 3
S0 S1 S2 S3 S4 S5 A8A9 A0-A7 D0-D7
0 1 0 0 1 11
1 253
Bit mask
1 0 1 1 0 01
1 254
PSC byte 1
1 0 1 1 0 01
1 255
PSC byte 2
Operation
Write error counter
Verify 1st PSC byte
Verify 2nd PSC byte
Semiconductor Group
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