SLX24C64 Datasheet, PDF (12/26 Pages) Siemens Semiconductor Group – 64 Kbit 8192 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus

SLx 24C64
5.2 Page Write
Address Setting
Transmission of Data
Programming Cycle
The page write procedure is the same as the byte write
procedure up to the first data byte. In a page write instruction
however, entry of the EEPROM address bytes AHI/ALO are
followed by a sequence of one to a maximum of 32 data bytes
with the new data to be programmed. These bytes are
transferred to the internal page buffer of the EEPROM.
The first entered data byte will be stored according to the
EEPROM address n given by AHI (A8 to A12) and ALO (A0 to
A7). The internal address counter is incremented
automatically after the entered data byte has been
acknowledged. The next data byte is then stored at the next
higher EEPROM address. EEPROM addresses within the
same page have common page address bits A5 through A12.
Only the respective five least significant address bits A0
through A4 are incremented, as all data bytes to be
programmed simultaneously have to be within the same page.
Writing over the page border will cause the address counter to
roll over to the first address of the page.
The master stops data entry by applying a STOP condition,
which also starts the internally timed erase/write cycle. In the
first step, all selected bytes are erased to “1”. With the next
internal step, the addressed bytes are written according to the
contents of the page buffer.
Those bytes of the page that have not been addressed are not included in the
programming.
S
T _Command
Bus Activity ^{A Byte}
Master ^R CSW
T
EEPROM
Address
AHI
EEPROM
Address
ALO
Data
Byte n
Data ... Data ^S
Byte n+1 Byte n+31 ^T
O
P
SDA Line S
0
P
Bus Activity
EEPROM
A
A
A
A
A
A
C
C
C
C
C
C
K
K
K
K
K
K
IED02519
Figure 8
Page Write Sequence
Semiconductor Group
12
Preliminary 1998-07-27