TLE4278G Datasheet, PDF (11/18 Pages) Siemens Semiconductor Group – 5-V Low-Drop Fixed Voltage Regulator

TLE 4278 G
Reset Timing
The power-on reset delay time is defined by the charging time of an external capacitor
C_d which can be calculated as follows:
C_d = (∆t_d × I_d)/∆V
Definitions: C_d = delay capacitor
∆t_d = delay time
I_d = charge current, typical 5 mA
∆V = V_DU, typical 1.9 V
V_DU = upper delay switching threshold at C_d for reset delay time
The reset reaction time t_rr is the time it takes the voltage regulator to set the reset out
LOW after the output voltage has dropped below the reset threshold. It is typically 1 µs
for delay capacitor of 47 nF. For other values for C_d the reaction time can be estimated
using the following equation:
t_rr ≈ 20 s/F × C_d
V_Ι
V _RT
V_Q
V_D
t_d
t _RR
< t _RR
dV
dt
=
Ι_d
C_D
V_DT
V_ST
V _RO
Power-on-Reset
Thermal
Shutdown
Voltage Dip
at Input
Undervoltage
Secondary Overload
Spike at Output
AED01542
Figure 5
Reset Timing (Watchdog Disabled)
Semiconductor Group
11
1998-11-01