SCF5740 Datasheet, PDF (11/12 Pages) Siemens Semiconductor Group – 0.270” 4-Character, 5x7 Dot Matrix Serial Input Dot Addressable Intelligent Display

V_CC
40 P3.0 ¹⁰
18 _XTAL2
P3.1
P3.6
11
16
P0.0 ³⁹
19 ^XTAL1
U1
V_CC
8031
1 _RST
9 _P1.0
20
V_CC
15 SDCLK _GND
13 _LD
DATA
ID
19 ^RST
V_CC ¹⁰
CLKSEL ²¹
2 ^GND CLK I/O ⁸
14 ^{22 µF}
TAN
+
.01 µF
Figure 11. Display Interface to Siemens/Intel 8031 Microprocessor (using one bit of parallel port as serial port)
VCC
VCC
38
40
OSC1
PA0 ¹¹
PA1 ¹⁰
SCLK ³³
MOSI ³²
39 ^OSC2
VCC
U1
68HC05C4
1 _RST
9 _PA2
20
15 SDCLK GND
13 _LD
DATA
ID
19 ^RST
VCC ¹⁰
CS ²¹
2 ^GND CLK I/O ⁸
14 _{22 µF}
+TAN
.01 µF
Figure 12. Display Interface with Motoroal 68HC05C4 Microprocessor (using SPI Port)
RST
VCC
RST CLK I/O
CLK SEL
Intelligent Display
DATA SDCLK
LOAD
14 more displays
in between
RST CLK I/O
CLK SEL
Intelligent Display
DATA SDCLK
LOAD
DATA
SDCLK
A0
A1
A2
A3
LD
0
Chip
Address
Decoder 15
CE
Address Decode 1–14
Figure 13. Cascading Multiple Displays
Multiple displays can be cascaded using the CLK SEL and CLK I/O pins (Figure 13). The display designated as the Master-
Clock source should have its CLK SEL pin tied high and the slaves should have their CLK SEL pins tied low. All CLK I/O pins
should be tied together. One display CLK I/O can drive 15 slave CLK I/Os. Use RST to synchronize all display counters.
2–210
SCF5740/2/4