SDA2546-5 Datasheet, PDF (1/12 Pages) Siemens Semiconductor Group – Nonvolatile Memory 4-Kbit E2PROM with I2C Bus Interface

Nonvolatile Memory 4-Kbit E²PROM
with I²C Bus Interface
Preliminary Data
Features
q Word-organized reprogrammable nonvolatile memory
in n-channel floating-gate technology (E²PROM)
q 512 × 8-bit organization
q Supply voltage 5 V
q Serial 2-line bus for data input and output (I²C Bus)
q Reprogramming mode, 10 ms erase/write cycle
q Reprogramming by means of on-chip control (without
external control)
q The end of the programming cycle can be checked
q Data retention in excess of 10 years
q More than 10⁴ reprogramming cycles per address
Type
SDA 2546-5
Ordering Code
Q67100-H5096
SDA 2546-5
MOS IC
P-DIP-8-1
Package
P-DIP-8-1
Circuit Description
I²C Bus Interface
The I²C Bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits.
It consists of a data line SDA and a clock line SCL. The data line requires an external pull-up resistor
to V_CC (open drain output stages).
The possible operational states of the I²C Bus are shown in figure 1. In the quiescent state, both
lines SDA and SCL are high, i.e. the output states are disabled. As long as SCL remains "1",
information changes on the data bus indicate the start or the end of a data transfer between two
components. The transition on SDA from "1" to "0" is a start condition, the transition from "0" to "1"
a stop condition. During a data transfer the information on the data bus will only change when the
clock line SCL is "0". The information on SDA is valid as long as SCL is "1".
In conjunction with an I²C Bus system, the device can operate as a receiver, and as a transmitter
(slave receiver/listener, or slave transmitter/talker). Between the falling edge of the eighth
transmission pulse and a ninth acknowledge clock pulse, the device sets the SDA-line to low as a
reception confirmation, if the chip select conditions have been met. During the output of data, the
data output of the memory becomes high, during the ninth clock pulse (acknowledge master).
The signal timing required for the operation of the I²C Bus is summarized in figure 2.
Semiconductor Group
29
07.94