HDM9020 Datasheet, PDF (4/5 Pages) Shoulder Electronics Limited. – Frequency Synthesizer

Frequency Synthesizer
HDM9020
4.Electrical Specifications
Test conditions: VCC VCO=+5V, VCC PLL=+3.3V, Step Size=30KHz,
Reference Freq.=30MHz, Reference Level=1Vp-p, Reference P.Noise=-125dBc/Hz(@100Hz),
Impedance = 50Ω, Charge Pump Current=2.55mA, LD=Digital Lock Detect.
Parameters
Min. Typ. Max. Units Cpk
Frequency Range
Over temperature
970 -
1073 MHz
Step Size
-
30 -
KHz
PFD Frequency
Setting Time
Output Power
Within ±1KHz
@+25^oC
@-40 ^oC to +85 ^oC
@100Hz offset
@1KHz offset
15
MHz
-
-
-1
0
15 mSec
+1 dBm ≥TBD
-2 0
+2 dBm
-
-80 -75
-
-88 -83
≥TBD
≥TBD
SSB Phase Noise
@10 KHz offset
-
-95 -88 dBc/Hz
@100 KHz offset
-
-123 -118
Spurious Suppression
@1MHz offset
-
@Step Size @ ±15KHz
-
@Step Size @ ±30KHz
-
@PFK Comparison frequency offset @ ±15MHz -
-143 -139
-
-60
-
-60
-
-70 dBc
@Referenct frequency offset
-
-80 -70
@Non-Harmonic
-
-90 -85
Harmonic Suppression
-
-20 -15 dBc
VCO Power Supply
+4.85 +5.00 +5.15 V
PLL Power Supply
+3.10 +3.30 +3.50 V
VCO Supply Current
-
30 36 mA
PLL Supply Current
-
15 23 mA
Frequency
-
30 -
MHz
Reference Input
Amplitude (Square wave)
Input inpedance
-
1
-
V_p-p
-
100 -
KΩ
Phase Noise @ 100Hz offset
RF Output port Impedance
-
-125 -
dBc/Hz
-
50 -
Ω
Input Logic Level
Input high voltage
Input low voltage
2.8 -
-
-
3.4 V
0.7 V
PLL Lock
Locked
2.7 -
3.5 V
Monitor Output
Unlocked
-
-
0.4 V
Frequency Synthesizer PLL
ADF4153
PLL Programming
3-wire serial 3V CMOS
R0_Register
(MSB) 000100011100010000101000 (LSB)
Register Map
R1_Register
(MSB) 000100001000011111010001 (LSB)
@ 1072.98MHz
R2_Register
(MSB) 0000001111000010 (LSB)
R3_Register
(MSB) 00000000011 (LSB)
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