LR38617 Datasheet, PDF (4/9 Pages) Sharp Electrionic Components – Timing Generator IC for 3 300 k/3 370 k-pixel CCDs

LR38617
PIN NO. SYMBOL IO SYMBOL POLARITY
PIN NAME
14 BCPX
O3
Optical black clamp
pulse output
15 CLPX
O3
Clamp pulse output
16 ADCK
17 GND
O6MA3
AD clock output
–
– Ground
18 FCDS O6MA3
CDS pulse output 1
19 FS
O6MA3
CDS pulse output 2
20 VDD3
–
– Power supply
21 ACLX
ICU3 – All clear input
22 RS
23 GND
24 TIN
25 CKI
26 CKO
27 CLK
O6MA3
S/H pulse output
–
IC3
OSCI3
– Ground
– Test input
– Clock input
OSCO3 – Clock output
O6MA3
Clock output
28 DCLK O6MA3
Clock output
29 VD
30 VDD3
31 GND
Vertical reference
IC3
pulse input
–
– Power supply
–
– Ground
DESCRIPTION
A pulse to clamp the optical black signal.
This pulse is controlled by serial data BCPCNT.
BCPCNT = H; This pulse stays high during the
absence of effective pixels within the
vertical blanking or during the
sweepout signal.
BCPCNT = L; This pulse stays high during sweepout
signal.
A pulse to clamp the dummy outputs of the CCD signal.
This pulse stays high during the sweepout period.
An output pin for AD converter. The output phase of
ADCK is selected by serial data in 90˚ steps.
A grounding pin.
A pulse to clamp the feed-through level for the CCD.
The output phase and output polarity of FCDS are
selected by serial data.
A pulse to sample-hold the signal for the CCD.
The output phase and output polarity of FS are selected
by serial data.
Supply of +3.3 V power.
An input pin for resetting all internal circuits at power-on.
Connect to VDD3 through the diode and GND through
the capacitor.
A pulse to sample-hold the signal for the CDS circuit.
The output phase and output polarity of RS are selected
by serial data.
A grounding pin.
A test pin. Set to L level in normal mode.
An input pin for reference clock oscillation.
The frequency is 36.00 MHz.
An output pin for reference clock oscillation.
The output is the inverse of CKI (pin 25).
An output pin to generate HD and VD pulses.
The frequency is 18.00 MHz.
An output pin for DSP IC. The frequency is 18.00 MHz.
The output phase of DCLK is selected by serial data in
90˚ steps.
An input pin for reference of vertical pulse.
Connect to VD pin of DSP IC.
Supply of +3.3 V power.
A grounding pin.
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