LH28F800BJE-PBTL90 Datasheet, PDF (29/47 Pages) Sharp Electrionic Components – 8M (x8/x16) Flash Memory

LHF80J04
27
5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
The device will often be used in large memory arrays.
SHARP provides three control inputs to accommodate
multiple memory connections. Three-line control provides
for:
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will not
occur.
To use these control inputs efficiently, an address decoder
should enable CE# while OE# should be connected to all
memory devices and the system’s READ# control line.
This assures that only selected memory devices have
active outputs while deselected memory devices are in
standby mode. RP# should be connected to the system
POWERGOOD signal to prevent unintended writes during
system power transitions. POWERGOOD should also
toggle during system reset.
5.2 RY/BY# and WSM Polling
RY/BY# is an open drain output that should be connected
to V_CC by a pull up resistor to provides a hardware method
of detecting block erase, full chip erase, word/byte write
and lock-bit configuration completion. It transitions low
after block erase, full chip erase, word/byte write or lock-
bit configuration commands and returns to V_OH (while
RY/BY# is pull up) when the WSM has finished executing
the internal algorithm.
RY/BY# can be connected to an interrupt input of the
system CPU or controller. It is active at all times. RY/BY#
is also High Z when the device is in block erase suspend
(with word/byte write inactive), word/byte write suspend
or reset modes.
5.3 Power Supply Decoupling
Flash memory power switching characteristics require
careful device decoupling. System designers are interested
in three supply current issues; standby current levels,
active current levels and transient peaks produced by
falling and rising edges of CE# and OE#. Transient current
magnitudes depend on the device outputs’ capacitive and
inductive loading. Two-line control and proper decoupling
capacitor selection will suppress transient voltage peaks.
Each device should have a 0.1µF ceramic capacitor
connected between its V_CC and GND and between its
V_CCW and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to package
leads. Additionally, for every eight devices, a 4.7µF
electrolytic capacitor should be placed at the array’s power
supply connection between V_CC and GND. The bulk
capacitor will overcome voltage slumps caused by PC
board trace inductance.
5.4 V_CCW Trace on Printed Circuit Boards
Updating flash memories that reside in the target system
requires that the printed circuit board designer pay
attention to the V_CCW Power supply trace. The V_CCW pin
supplies the memory cell current for word/byte writing
and block erasing. Use similar trace widths and layout
considerations given to the V_CC power bus. Adequate
V_CCW supply traces and decoupling will decrease V_CCW
voltage spikes and overshoots.
5.5 V_CC, V_CCW, RP# Transitions
Block erase, full chip erase, word/byte write and lock-bit
configuration are not guaranteed if V_CCW falls outside of a
valid V_CCWH1/2 range, V_CC falls outside of a valid 2.7V-
3.6V range, or RP#≠V_IH. If V_CCW error is detected, status
register bit SR.3 is set to "1" along with SR.4 or SR.5,
depending on the attempted operation. If RP# transitions
to V_IL during block erase, full chip erase, word/byte write
or lock-bit configuration, RY/BY# will remain low until
the reset operation is complete. Then, the operation will
abort and the device will enter reset mode. The aborted
operation may leave data partially altered. Therefore, the
command sequence must be repeated after normal
operation is restored. Device power-off or RP# transitions
to V_IL clear the status register.
The CUI latches commands issued by system software and
is not altered by V_CCW or CE# transitions or WSM
actions. Its state is read array mode upon power-up, after
exit from reset mode or after V_CC transitions below V_LKO.
Rev. 1.27