LRS1386 Datasheet, PDF (23/114 Pages) Sharp Electrionic Components – STACKED CHIP 64M FLASH AND 8M SRAM

LRS1386
21
12.3 Write Cycle (F-WE / F-CE Controlled)^(1,2)
(T_A = -25°C to +85°C, F-V_CC = 2.7V to 3.3V)
Symbol
Parameter
Notes Min. Max.
Unit
t_PHWL (t_PHEL) F-RST High Recovery to F-WE (F-CE) Going Low
t_ELWL (t_WLEL) F-CE (F-WE) Setup to F-WE (F-CE) Going Low
t_WLWH (t_ELEH) F-WE (F-CE) Pulse Width
t_DVWH (t_DVEH) Data Setup to F-WE (F-CE) Going High
t_AVWH (t_AVEH) Address Setup to F-WE (F-CE) Going High
t_WHEH (t_EHWH) F-CE (F-WE) Hold from F-WE (F-CE) High
t_WHDX (t_EHDX) Data Hold from F-WE (F-CE) High
t_WHAX (t_EHAX) Address Hold from F-WE (F-CE) High
t_WHWL (t_EHEL) F-WE (F-CE) Pulse Width High
t_SHWH (t_SHEH) F-WP High Setup to F-WE (F-CE) Going High
t_VVWH (t_VVEH) F-V_PP Setup to F-WE (F-CE) Going High
t_WHGL (t_EHGL) Write Recovery before Read
t_QVSL
F-WP High Hold from Valid SRD, F-RY/BY High - Z
t_QVVL
F-V_PP Hold from Valid SRD, F-RY/BY High - Z
t_WHR0 (t_EHR0) F-WE (F-CE) High to SR.7 Going "0"
t_WHRL (t_EHRL) F-WE (F-CE) High to F-RY/BY Going Low
3
150
ns
4
0
ns
4
60
ns
8
40
ns
8
50
ns
0
ns
0
ns
0
ns
5
30
ns
3
0
ns
3
200
ns
30
ns
3, 6
0
ns
3, 6
0
ns
3, 7
t_AVQV+50
ns
3
100
ns
Notes:
1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and OTP
program operations are the same as during read-only operations. See the AC Characteristics for read cycle.
2. A write operation can be initiated and terminated with either F-CE or F-WE.
3. Sampled, not 100% tested.
4. Write pulse width (t_WP) is defined from the falling edge of F-CE or F-WE (whichever goes low last) to the rising edge of
F-CE or F-WE (whichever goes high first). Hence, t_WP=t_WLWH=t_ELEH=t_WLEH=t_ELWH.
5. Write pulse width high (t_WPH) is defined from the rising edge of F-CE or F-WE (whichever goes high first) to the falling
edge of F-CE or F-WE (whichever goes low last). Hence, t_WPH=t_WHWL=t_EHEL=t_WHEL=t_EHWL.
6. F-V_PP should be held at F-V_PP=V_PPH1/2 until determination of block erase, full chip erase, (page buffer) program or OTP
program success (SR.1/3/4/5=0).
7. t_WHR0 (t_EHR0) after the Read Query or Read Identifier Codes/OTP command=t_AVQV+100ns.
8. See 5.1 Command Definitions for valid address and data for block erase, full chip erase, (page buffer) program, OTP
program or lock bit configuration.