LH540205 Datasheet, PDF (2/17 Pages) Sharp Electrionic Components – CMOS 8192 x 9 Asynchronous FIFO

LH540205
FUNCTIONAL DESCRIPTION (cont’d)
The Reset (RS) control signal returns the LH540205
to an initial state, empty and ready to be filled. An
LH540205 should be reset during every system power-up
sequence. A reset operation causes the internal FIFO-
memory-array write-address pointer, as well as the read-
address pointer, to be set back to zero, to point to the
LH540205’s first physical memory location. Any informa-
tion which previously had been stored within the
LH540205 is not recoverable after a reset operation.
A cascading (depth-expansion) scheme may be imple-
mented by using the Expansion In (XI) input signal and
the Expansion Out (XO/HF) output signal. This scheme
CMOS 8192 × 9 Asynchronous FIFO
allows a deeper ‘effective FIFO’ to be implemented by
using two or more individual LH540205 devices, without
incurring additional latency (‘fallthrough’ or ‘bub-
blethrough’) delays, and without the necessity of storing
and retrieving any given data word more than once. In this
cascaded operating mode, one LH540205 device must
be designated as the ‘first-load’ or ‘master’ device, by
grounding its First-Load (FL/RT) control input;the remain-
ing LH540205 devices are designated as ‘slaves,’ by tying
their FL/RT inputs HIGH. Because of the need to share
control signals on pins, the Half-Full Flag and the retrans-
mission capability are not available for either ‘master’ or
‘slave’ LH540205 devices operating in cascaded mode.
RS
RESET
LOGIC
DATA INPUTS
D₀ - D₈
INPUT
OUTPUT
W
PORT
PORT
R
CONTROL
DUAL-PORT
CONTROL
WRITE
POINTER
RAM
ARRAY
READ
POINTER
8192 x 9
...
DATA OUTPUTS
Q₀ - Q₈
FLAG
EF
LOGIC
FF
FL/RT
XI
EXPANSION
LOGIC
XO/HF
Figure 2. LH540205 Block Diagram
540205-1
2