SM6010 Datasheet, PDF (1/2 Pages) Sharp Electrionic Components – 16-Bit Single- Chip Microcomputer

PRODUCT INFORMATION
®
SM6010 16-Bit Single-
Chip Microcomputer
APPLICATIONS:
•
Pager
•
PDA
•
Digital Camera
Integrated Circuits
Group
FEATURES
• CPU
– General purpose registers 16-bit × 16
– 62 basic instruction (bit manipulation instructions suitable
for controlling, bit transfer instructions, bit branch instruc-
tions, high speed multiplication and division instructions
(16-bits × 16-bits, 16-bits ÷ 16-bits, 32-bits ÷ 16-bits)).
– 10 addressing modes
– 16M of address space
– An interrupt request starts a high performance automatic
data transfer (DTS). Appropriate settings of interrupts and
registers enable hardware automatic data transfer. Various
functions can be operated successively and the resultant data
can also be successfully be stored.
– System clock cycle
• 0.133 µs MIN. (V_DD = 4.5 V to 5.5 V at 30 MHz main
clock cycle)
• 0.2 µs MIN. (V_DD = 2.7 V to 5.5 V, at 20 MHz main
clock cycle)
– Selectable system clocks divided by 2 up to 16 main clocks
for low power operation
• Memory interface
– 16-bit external address bus
– Optional A24 to A16 capable of 32M for data and 16M for code
• Built-in main clock oscillator for system clock
• Built-in sub clock oscillator for real time clock
• 21 total software interrupts
– 16 maskable interrupts (8 external, 8 internal)
– 5 nonmaskable interrupts
– Nonmaskable interrupts, when used in conjunction with
BST instruction, can trigger the software reset.
• Standby function: Halt mode/Stop mode
• I/O ports × 40
– Inputs ports × 8 (also serve as A/D input)
– I/O ports × 32 (also serve as functional pins)
• LCD controller
– Frame buffer resides in system memory
– LCD display modes
• 1 bit/pixel binary mode
• Gray mode, 4-level 2-bits/pixel and 16-level 4-bits/pixel
• LCD display data, 4, 2, 1-bit transfer
• Maximum resolution
– Horizontal
• 1,024 pixels in binary mode
• 512 pixels in 4-level gray shade mode,
• 256 pixels in 16-level gray shade mode
– Vertical: 256 lines
• Support vertical display screen
• DMA: Main memory → LCDC buffer
• Real time clock
– Using 32.768 kHz clock
– Seconds, minutes, hours, days
– 1-minute or 1-second or 1-day interrupt
– Alarm register
• Watchdog timer (overrun detect timer)
– 8-bit × 1
– 51 µs up to 209 ms at 10 MHz (internal)
• Serial interface: Serial interface × 1 channel
• SCI (Serial Communication Interface)
– Programmable between UART and synchronized
– UART
• Only TxD, RxD supported
• Built-in baud rate generator
• Stop bit: 1, 2-bit
• Even, odd and non-parity bits
• Error detection frame, parity, overrun
– Synchronized
• 8-bit data
• Error detection: Overrun
• SIR (Serial Infra-Red Interface)
– Using UART
– IrDA SIR (version 1.0) compatible
– Sharp DASK SIR compatible
– From 2.4 kb/s up to 115.2 kb/s IrDA data rate
– From 2.4 kb/s up to 57.6 kb/s DASK data rate
The information for this document is from the Microcomputer Databook, issued in March 1997.
Copyright ©1998, Sharp Electronics Corp. All rights reserved. All tradenames are the registered property of their respective owners. Specifications are subject to change without notice.
SMT98028