LRS1341 Datasheet, PDF (1/24 Pages) Sharp Electrionic Components – Stacked Chip 16M Flash Memory and 2M SRAM

Data Sheet
LRS1341/LRS1342
Stacked Chip
16M Flash Memory and 2M SRAM
FEATURES
• Flash Memory and SRAM
• Stacked Die Chip Scale Package
• 72-ball CSP (FBGA072-P-0811) plastic package
• Power supply: 2.7 V to 3.6 V
• Operating temperature: -25°C to +85°C
• Flash Memory
– Access time (MAX.): 100 ns
– Operating current (MAX.):
The current for F-V_CC pin
– Read: 25 mA (t_CYCLE = 200 ns)
– Word write: 17 mA
– Block erase: 17 mA
– Deep power down current (the current for
F-V_CC pin): 10 µA (MAX. F-CE ≥ F-V_CC - 0.2 V,
F-RP ≤-0.2 V, F-V_PP ≤0.2 V)
– Optimized array blocking architecture
– Two 4K-word boot blocks
– Six 4K-word parameter blocks
PIN CONFIGURATION
72-BALL FBGA
INDEX
– Thirty-one 32K-word main blocks
– Top/Bottom boot location versions
– Extended cycling capability
– 100,000 block erase cycles
– Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read
• SRAM
– Access time (MAX.): 85 ns
– Operating current (MAX.):
– 45 mA
– 8 mA (t_RC, t_WC = 1 µs)
– Standby current: 45 µA (MAX.)
– Data retention current: 35 µA (MAX.)
DESCRIPTION
The LRS1341/LRS1342 is a combination memory
organized as 1,048,576 × 16-bit flash memory and
131,072 × 16-bit static RAM in one package.
TOP VIEW
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2
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7
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9 10 11 12
A NC NC NC A₁₁ A₁₅ A₁₄ A₁₃ A₁₂ GND NC NC NC
B
A₁₆ A₈ A₁₀ A₉ DQ₁₅ S-WE DQ₁₄ DQ₇
C
F-WE ^F-RY/
BY
T₁
T₃ DQ₁₃ DQ₆ DQ₄ DQ₅
D
GND F-RP T₂ T₄ DQ₁₂ S-CE₂ S-V_CC F-V_CC
E
F-WP F-V_PP F-A₁₉ DQ₁₁ T₅ DQ₁₀ DQ₂ DQ₃
F
S-LB S-UB S-OE NC DQ₉ DQ₈ DQ₀ DQ₁
G
F-A₁₈ F-A₁₇ A₇ A₆ A₃ A₂ A₁ S-CE₁
H NC NC NC A₅ A₄ A₀ F-CE GND F-OE NC NC NC
NOTE: Two NC pins at the corner are connected.
Figure 1. LRS1341/LRS1342 Pin Configuration
LRS1342-1
Data Sheet
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