LH6V4256 Datasheet, PDF (1/18 Pages) Sharp Electrionic Components – CMOS 1M (256K x 4) Dynamic RAM

LH6V4256
FUNCTION
• 262,144 words × 4 bit
• Access time: 100 ns (MAX)
• Cycle time: 190 ns (MIN)
• Fast page mode cycle time: 60 ns (MIN)
• Power supply: +3.3 V ±0.3 V
• Power consumption (MAX):
Operating: 126 mW
Standby: 0.54 mW
• Built-in latch circuit for row-address,
column-address, and input data
• OE = Don’t care in early write operation
• RAS only refresh, hidden refresh, and
CAS before RAS refresh capability
• On-chip refresh counter
• 512 refresh cycle/8 ms
• Packages:
20-pin, 300-mil DIP
26-pin, 300-mil SOJ
28-pin, 8 × 13 mm² TSOP (Type I)
CMOS 1M (256K × 4) Dynamic RAM
DESCRIPTION
The LH6V4256 is a 262,144 word × 4-bit dynamic
RAM which allows fast page mode access. The
LH6V4256 is fabricated on SHARP’s advanced CMOS
double-level polysilicon gate technology. With its input
multiplexed and packaged in the standard 20-pin DIP,
26-pin SOJ, or 28-pin TSOP (I) packages, it is easy to
realize memory systemswith low power dissipation and
large memory capacity. The LH6V4256 operates on a
single +3.3 V power supply and the built-in biasing
voltage generator circuit.
PIN CONNECTIONS
20-PIN DIP
TOP VIEW
I/O₁ 1
I/O₂ 2
WE 3
RAS 4
NC 5
A₀ 6
A₁ 7
A₂ 8
A₃ 9
V_CC 10
20 V_SS
19 I/O ₄
18 I/O₃
17 CAS
16 OE
15 A₈
14 A₇
13 A₆
12 A₅
11 A₄
6V4256-1
Figure 1. Pin Connections for DIP Package
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