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| LH5P8129 Datasheet, PDF (1/14 Pages) Sharp Electrionic Components – CMOS 1M (128K x 8) CS-Control Pseudo-Static RAM | |||
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LH5P8129
CMOS 1M (128K Ã 8)
CS-Control Pseudo-Static RAM
FEATURES
⢠131,072 à 8 bit organization
⢠Access times (MAX.): 60/80/100 ns
⢠Cycle times (MIN.): 100/130/160 ns
⢠Single +5 V power supply
⢠Pin compatible with 1M standard SRAM
⢠Power consumption:
Operating: 572/385/275 mW (MAX.)
Standby (TTL level): 5.5 mW (MAX.)
Standby (CMOS level): 1.1 mW (MAX.)
⢠TTL compatible I/O
⢠Available for auto-refresh and self-refresh
modes
⢠512 refresh cycles/8 ms
⢠Packages:
32-pin, 600-mil DIP
32-pin, 525-mil SOP
32-pin, 8 Ã 20 mm2 TSOP (Type I)
DESCRIPTION
The LH5P8129 is a 1M bit Pseudo-Static RAM
organized as 131,072 Ã 8 bits. It is fabricated using
silicon-gate CMOS process technology.
A PSRAM uses on-chip refresh circuitry with a DRAM
memory cell for pseudo static operation which elimi-
nates external clock inputs, while considering the pinout
compatibility with industry standard SRAMs. The
advantage is the cost savings realized with the lower
cost PSRAM.
The LH5P8129 PSRAM has a built-in oscillator, which
makes it easy to refresh memories without external
clocks.
PIN CONNECTIONS
32-PIN DIP
32-PIN SOP
TOP VIEW
RFSH 1
A16
2
A14
3
A12
4
A7
5
A6
6
A5
7
A4
8
A3
9
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
GND 16
32 VCC
31 A15
30 CS
29 R/W
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
5P8129-1
Figure 1. Pin Connections for DIP and
SOP Packages
32-PIN TSOP (Type I)
TOP VIEW
A11
1
A9
2
A8
3
A13
4
R/W 5
CS 6
A15
7
VCC
8
RFSH 9
A16 10
A14 11
A12 12
A7 13
A6 14
A5 15
A4 16
32 OE
31 A10
30 CE
29 I/O7
28 I/O6
27 I/O5
26 I/O4
25 I/O3
24 GND
23 I/O2
22 I/O1
21 I/O0
20 A0
19 A1
18 A2
17 A3
NOTE: Reverse bend available on request.
5P8129-2
Figure 2. Pin Connections for TSOP Package
1
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