LH5P8128 Datasheet, PDF (1/13 Pages) Sharp Electrionic Components – CMOS 1M (128K x 8) Pseudo-Static RAM

LH5P8128
CMOS 1M (128K × 8) Pseudo-Static RAM
FEATURES
• 131,072 × 8 bit organization
• Access times (MAX.): 60/80/100 ns
• Cycle times (MIN.): 100/130/160 ns
• Single +5 V power supply
• Power consumption:
Operating: 572/385/275 mW (MAX.)
Standby (CMOS level): 1.1 mW (MAX.)
• TTL compatible I/O
• Available for auto-refresh and self-refresh
modes
• 512 refresh cycles/8 ms
• Compatible with standard 1M
SRAM pinout
• Packages:
32-pin, 600-mil DIP
32-pin, 525-mil SOP
32-pin, 8 × 20 mm² TSOP (Type I)
DESCRIPTION
The LH5P8128 is a 1M bit Pseudo-Static RAM
organized as 131,072 × 8 bits. It is fabricated using
silicon-gate CMOS process technology.
A PSRAM uses on-chip refresh circuitry with a DRAM
memory cell for pseudo static operation which elimi-
nates external clock inputs, while having the same
pinout as industry standard SRAMs. Moreover, due to
the functional similarities between PSRAMs and
SRAMs, existing 128K × 8 SRAM sockets can be filled
with the LH5P8128 with little or no changes. The
advantage is the cost savings realized with the lower
cost PSRAM.
The LH5P8128 PSRAM has the ability to fill the gap
between DRAM and SRAM by offering low cost, low
power standby and a simple interface.
PIN CONNECTIONS
32-PIN DIP
32-PIN SOP
TOP VIEW
RFSH 1
A₁₆
2
A₁₄
3
A₁₂
4
A₇
5
A₆
6
A₅
7
A₄
8
A₃
9
A₂ 10
A₁ 11
A₀ 12
I/O₀ 13
I/O₁ 14
I/O₂ 15
GND 16
32 V_CC
31 A₁₅
30 CE₂
29 R/W
28 A₁₃
27 A₈
26 A₉
25 A₁₁
24 OE
23 A₁₀
22 CE₁
21 I/O₇
20 I/O₆
19 I/O₅
18 I/O₄
17 I/O₃
5P8128-1
Figure 1. Pin Connections for DIP and
SOP Packages
32-PIN TSOP (Type I)
A₁₁
1
A₉
2
A₈
3
A₁₃
4
R/W 5
CE₂ 6
A₁₅
7
V_CC
8
RFSH 9
A₁₆ 10
A₁₄ 11
A₁₂ 12
A₇ 13
A₆ 14
A₅ 15
A₄ 16
32 OE
31 A₁₀
30 CE₁
29 I/O₇
28 I/O₆
27 I/O₅
26 I/O₄
25 I/O₃
24 GND
23 I/O₂
22 I/O₁
21 I/O₀
20 A₀
19 A₁
18 A₂
17 A₃
NOTE: Reverse bend available on request.
5P8128-1A
Figure 2. Pin Connections for TSOP Package
1