LH5496 Datasheet, PDF (1/16 Pages) Sharp Electrionic Components – CMOS 512 x 9 FIFO

LH5496/96H
CMOS 512 × 9 FIFO
FEATURES
• Fast Access Times:
15 */20/25/35/50/65/80 ns
• Full CMOS Dual Port Memory Array
• Fully Asynchronous Read and Write
• Expandable-in Width and Depth
• Full, Half-Full, and Empty Status Flags
• Read Retransmit Capability
• TTL Compatible I/O
• Packages:
28-Pin, 300-mil PDIP
28-Pin, 600-mil PDIP
32-Pin PLCC
• Pin and Functionally Compatible with IDT7201
FUNCTIONAL DESCRIPTION
The LH5496/96H are dual port memories with internal
addressing to implement a First-In, First-Out algorithm.
Through an advanced dual port architecture, they provide
fully asynchronous read/write operation. Empty, Full, and
Half-Full status flags are provided to prevent data over-
flow and underflow. In addition, internal logic provides for
unlimited expansion in both word size and depth.
Read and write operations automatically access se-
quential locations in memory in that data is read out in the
same order that it was written, that is on a First-In,
First-Out basis. Since the address sequence is internally
predefined, no external address information is required
for the operation of this device. A ninth data bit is provided
for parity or control information often needed in commu-
nication applications.
Empty, Full, and Half-Full status flags monitor the
extent to which data has been written into the FIFO, and
prevent improper operations (i.e., Read if the FIFO is
empty, or Write if the FIFO is full). A retransmit feature
resets the Read address pointer to its initial position,
thereby allowing repetitive readout of the same data.
Expansion In and Expansion Out pins implement an
expansion scheme that allows individual FIFOs to be
cascaded to greater depth without incurring additional
latency (bubblethrough) delays.
* LH5496 only.
PIN CONNECTIONS
28-PIN PDIP
W1
D₈ 2
D₃ 3
D₂ 4
D₁ 5
D₀ 6
XI 7
FF 8
Q₀
9
Q₁ 10
Q₂ ¹¹
Q₃ 12
Q₈ 13
V_SS 14
TOP VIEW
28 V_CC
27 D₄
26 D₅
25 D₆
24 D₇
23 FL/RT
22 RS
21 EF
20 XO/HF
19 Q₇
18 Q₆
17 Q₅
16 Q₄
15 R
5496-1D
Figure 1. Pin Connections for PDIP Packages
32-PIN PLCC
TOP VIEW
4 3 2 1 32 31 30
D₂
5
D₁
6
D₀
7
XI 8
29 D₆
28 D₇
27 NC
26 FL/RT
FF 9
25 RS
Q₀ 10
24 EF
Q₁ 11
23 XO/HF
NC 12
22 Q₇
Q₂ 13
21 Q₆
14 15 16 17 18 19 20
5496-2D
Figure 2. Pin Connections for PLCC Package
1