LH5481 Datasheet, PDF (1/16 Pages) Sharp Electrionic Components – Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO

LH5481
LH5491
Cascadable 64 × 8 FIFO
Cascadable 64 × 9 FIFO
FEATURES
• Fastest 64 × 8/9 Cascadable FIFO
35/25/15 MHz
• Expandable in Word Width and
FIFO Depth
• Almost-Full/Almost-Empty and
Half-Full Flags
• Fully Independent Asynchronous
Inputs and Outputs
• LH5481 Output Enable forces Data
Outputs to High-Impedance State
• Pin-Compatible Replacements for Cypress
CY7C408A/09A or Logic Devices
L8C408/09 FIFOs
• Industry Standard Pinout
• Packages:
28-Pin, 300-mil DIP
28-Pin PLCC
FUNCTIONAL DESCRIPTION
The LH5481 and LH5491 are high-performance, asyn-
chronous First-In, First-Out (FIFO) memories organized
64 words deep by eight or nine bits wide. The eight-bit
LH5481 has an Output Enable (OE) function, which can
be used to force the eight data outputs (DO) to a high-im-
pedance state. The LH5491 has nine data outputs.
These FIFOs accept eight or nine-bit data at the Data
Inputs (DI). A Shift In (SI) signal writes the DI data into the
FIFO. A Shift Out (SO) signal shifts stored data to the Data
Outputs (DO). The Output Ready (OR) signal indicates
when valid data is present on the DO outputs.
If the FIFO is full and unable to accept more DI data,
Input Ready (IR) will not return HIGH, and SI pulses will
be ignored. If the FIFO is empty and unable to shift data
to the DO outputs, OR will not return HIGH, and SO
pulses will be ignored. The Almost-Full/Almost-Empty
(AFE) flag is asserted (HIGH) when the FIFO is almost-full
(56 words or more) or almost- empty (eight words or less).
The Half-Full (HF) flag is asserted (HIGH) when the FIFO
contains 32 words or more.
Reading and writing operations may be asynchronous,
allowing these FIFOs to be used as buffers between
digital machines of different operating frequencies. The
high speed makes these FIFOs ideal for high perform-
ance communication and controller applications.
PIN CONNECTIONS
28-PIN PDIP
AFE 1
HF 2
IR 3
SI 4
DI₀ 5
DI₁ 6
V_SS
7
DI₂ 8
DI₃ 9
DI₄ 10
DI₅ 11
DI₆ 12
DI₇ 13
NC/DI₈ 14
TOP VIEW
28 V_CC
27 MR
26 SO
25 OR
24 DO₀
23 DO₁
22 V_SS
21 DO₂
20 DO₃
19 DO₄
18 DO₅
17 DO₆
16 DO₇
15 OE/DO₈
5481-1D
Figure 1. Pin Connections for DIP Package
28-PIN PLCC
TOP VIEW
4 3 2 1 28 27 26
DI₀ 5
25 OR
DI₁ 6
24 DO₀
V_SS
7
23 DO₁
DI₂ 8
22 V_SS
DI₃ 9
21 DO₂
DI₄ 10
20 DO₃
DI₅ 11
19 DO₄
12 13 14 15 16 17 18
5481-2D
Figure 2. Pin Connections for PLCC Package
1