LH543611 Datasheet, PDF (1/57 Pages) Sharp Electrionic Components – 512 x 36 x 2 / 1024 x 36 x 2 Synchronous Bidirectional FIFO

LH543611/21
FEATURES
• ^{Pin-Compatible and Functionally}
Upwards-Compatible with Sharp LH5420 and
LH543601, but Deeper
• ^{Expanded Control Register that is Fully}
Readable as well as Writeable
• ^{Fast Cycle Times: 18/20/25/30/35 ns}
• ^{Improved Input Setup and Flag Out Timing}
• ^{Two 512 × 36-bit FIFO Buffers (LH543611) or}
Two 1024 × 36-bit FIFO Buffers (LH543621)
• ^{Full 36-bit Word Width}
• ^{Selectable 36/18/9-bit Word Width on Port B;}
Selection May be Changed Without Resetting
the BiFIFO
• ^{Programmable Byte-Order Reversal –}
‘Big-Endian ↔ Little-Endian Conversion’
• ^{Independently-Synchronized (‘Fully-Asynchronous’)}
Operation of Port A and Port B
• ^{‘Synchronous’ Enable-Plus-Clock Control at}
Both Ports
• ^{R/W, Enable, Request, and Address Control Inputs}
are Sampled on the Rising Clock Edge
• ^{Synchronous Request/Acknowledge ‘Handshake’}
Capability; Use is Optional
• ^{Device Comes Up Into a Known Default State at}
Reset; Programming is Allowed, but is not Required
• ^{Asynchronous Output Enables}
• ^{Five Status Flags per Port: Full, Almost-Full,}
Half-Full, Almost-Empty, and Empty
• ^{All Flags are Independently Programmable for}
Either Synchronous or Asynchronous Operation
• ^{Almost-Full Flag and Almost-Empty Flag Have}
Programmable Offsets
• ^{Mailbox Registers with Synchronized Flags}
• ^{Data-Bypass Function}
• ^{Data-Retransmit Function}
• ^{Automatic Byte Parity Checking with}
Programmable Parity Flag Latch
• ^{Programmable Byte Parity Generation}
• ^{Programmable Byte, Half-Word, or Full-Word}
Oriented Parity Operations
• ^{8 mA-I}OL ^{High-Drive Three-State Outputs with}
Built-In Series Resistor
• ^{TTL/CMOS-Compatible I/O}
• ^{Space-Saving PQFP and TQFP Packages}
BOLD = Additions over the 5420/3601 feature set
512 × 36 × 2 / 1024 × 36 × 2
Synchronous Bidirectional FIFO
FUNCTIONAL DESCRIPTION
The LH543611 and LH543621 contain two FIFO buff-
ers, FIFO #1 and FIFO #2. These operate in parallel, but
in opposite directions, for bidirectional data buffering.
FIFO #1 and FIFO #2 each are organized as 512 or 1024
by 36 bits. The LH543611 and LH543621 are ideal either
for wide unidirectional applications or for bidirectional
data applications; component count and board area are
reduced.
The LH543611 and LH543621 have two 36-bit ports,
Port A and Port B. Each port has its own port-synchro-
nous clock, but the two ports may operate asynchro-
nously relative to each other. Data flow is initiated at a port
by the rising edge of the appropriate clock; it is gated by
the corresponding edge-sampled enable, request, and
read/write control signals. At the maximum operating
frequency, the clock duty cycle may vary from 40% to
60%. At lower frequencies, the clock waveform may be
quite asymmetric, as long as the minimum pulse-width
conditions for clock-HIGH and clock-LOW remain satis-
fied; the LH543611 and LH543621 are fully-static parts.
Conceptually, the port clocks CK_A and CK_B are free-
running, periodic ‘clock’ waveforms, used to control other
signals which are edge-sensitive. However, there actually
is not any absolute requirement that these ‘clock’ wave-
forms must be periodic. An ‘asynchronous’ mode of op-
eration is possible, in one or both directions,
independently, if the appropriate enable and request in-
puts are continuously asserted, and enough aperiodic
‘clock’ pulses of suitable duration are generated by exter-
nal logic to cause all necessary actions to occur.
A synchronous request/acknowledge handshake
facility is provided at each port for FIFO data access. This
request/ acknowledge handshake resolves FIFO full and
empty boundary conditions, when the two ports are op-
erated asynchronously relative to each other.
FIFO status flags monitor the extent to which each
FIFO buffer has been filled. Full, Almost-Full, Half-Full,
Almost-Empty, and Empty flags are included for each
FIFO. Each of these flags may be independently pro-
grammed for either synchronous or asynchronous opera-
tion. Also, the Almost-Full and Almost-Empty flags are
programmable over the entire FIFO depth, but are auto-
matically initialized to eight locations from the respective
FIFO boundaries at reset. Adata block of 512 (LH543611)
or 1024 (LH543621) or fewer words may be retransmitted
any desired number of times.
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