LH543601 Datasheet, PDF (1/43 Pages) Sharp Electrionic Components – 256 x 36 x 2 Bidirectional FIFO

LH543601
FEATURES
• Fast Cycle Times: 20/25/30/35 ns
• Pin-Compatible and Functionally-Compatible
0.7µ-Technology Replacement for Sharp LH5420
• Two 256 × 36-bit FIFO Buffers
• Full 36-bit Word Width
• Selectable 36/18/9-bit Word Width on Port B
• Independently-Synchronized (‘Fully-Asynchronous’)
Operation of Port A and Port B
• ‘Synchronous’ Enable-Plus-Clock Control at
Both Ports
• R/W, Enable, Request, and Address Control Inputs
are Sampled on the Rising Clock Edge
• Synchronous Request/Acknowledge ‘Handshake’
Capability; Use is Optional
• Device Comes Up Into a Known Default State at
Reset; Programming is Allowed, but is not Required
• Asynchronous Output Enables
• Five Status Flags per Port: Full, Almost-Full,
Half-Full, Almost-Empty, and Empty
• Almost-Full Flag and Almost-Empty Flag are
Programmable
• Mailbox Registers with Synchronized Flags
• Data-Bypass Function
• Data-Retransmit Function
• Automatic Byte Parity Checking
• 8 mA-IOL High-Drive Three-State Outputs with
Built-In Series Resistor
• TTL/CMOS-Compatible I/O
• Space-Saving PQFP and TQFP Packages
• PQFP to PGA Package Conversion ¹
256 × 36 × 2 Bidirectional FIFO
FUNCTIONAL DESCRIPTION
The LH543601 contains two FIFO buffers, FIFO #1
and FIFO #2. These operate in parallel, but in opposite
directions, for bidirectional data buffering. FIFO #1 and
FIFO #2 each are organized as 256 by 36 bits. The
LH543601 is ideal either for wide unidirectional applica-
tions or for bidirectional data applications; component
count and board area are reduced.
The LH543601 has two 36-bit ports, Port A and Port B.
Each port has its own port-synchronous clock, but the two
ports may operate asynchronously relative to each other.
Data flow is initiated at a port by the rising edge of the
appropriate clock; it is gated by the corresponding edge-
sampled enable, request, and read/write control signals.
At the maximum operating frequency, the clock duty cycle
may vary from 40% to 60%. At lower frequencies, the
clock waveform may be quite asymmetric, as long as the
minimum pulse-width conditions for clock-HIGH and
clock-LOW remain satisfied; the LH543601 is a fully-static
part.
Conceptually, the port clocks CKA and CKB are free-
running, periodic ‘clock’ waveforms, used to control other
signals which are edge-sensitive. However, there actually
is not any absolute requirement that these ‘clock’ wave-
forms must be periodic. An ‘asynchronous’ mode of
operation is possible, in one or both directions, inde-
pendently, if the appropriate enable and request inputs
are continuously asserted, and enough aperiodic ‘clock’
pulses of suitable duration are generated by external logic
to cause all necessary actions to occur.
A synchronous request/acknowledge handshake
facility is provided at each port for FIFO data access. This
request/ acknowledge handshake resolves FIFO full and
empty boundary conditions, when the two ports are op-
erated asynchronously relative to each other.
FIFO status flags monitor the extent to which each
FIFO buffer has been filled. Full, Almost-Full, Half-Full,
Almost-Empty, and Empty flags are included for each
FIFO. The Almost-Full and Almost-Empty flags are pro-
grammable over the entire FIFO depth, but are automat-
ically initialized to eight locations from the respective FIFO
boundaries at reset. A data block of 256 or fewer words
may be retransmitted any desired number of times.
NOTE:
1. For PQFP-to-PGA conversion for thru-hole board designs, Sharp
recommends ITT Pomona Electronics’ SMT/PGA Generic
Converter model #5853.^® This converter maps the LH543601
132-pin PQFP to a generic 13 × 13, 132-pin PGA (100-mil
pitch). For more information, contact Sharp or ITT Pomona
Electronics at 1500 East Ninth Street, Pomona, CA 91766,
[phone].
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