LH540203 Datasheet, PDF (1/17 Pages) Sharp Electrionic Components – CMOS 2048 x 9 Asynchronous FIFO

LH540203
FEATURES
• Fast Access Times: 15/20/25/35/50 ns
• Fast-Fall-Through Time Architecture Based on
CMOS Dual-Port SRAM Technology
• Input Port and Output Port Have Entirely
Independent Timing
• Expandable in Width and Depth
• Full, Half-Full, and Empty Status Flags
• Data Retransmission Capability
• TTL-Compatible I/O
• Pin and Functionally Compatible with Sharp LH5498
and with Am/IDT/MS7203
• Control Signals Assertive-LOW for Noise Immunity
• Packages:
28-Pin, 300-mil PDIP
28-Pin, 300-mil SOJ *
32-Pin PLCC
PIN CONNECTIONS
28-PIN PDIP
28-PIN SOJ * W 1
D₈ 2
D₃ 3
D₂ 4
D₁ 5
D₀ 6
XI 7
FF 8
Q₀
9
Q₁ 10
Q₂ 11
Q₃ 12
Q₈ 13
V_SS 14
28 V_CC
TOP VIEW
27 D₄
26 D₅
25 D₆
24 D₇
23 FL/RT
22 RS
21 EF
20 XO/HF
19 Q₇
18 Q₆
17 Q₅
16 Q₄
15 R
540203-2D
Figure 1. Pin Connections for PDIP and
SOJ * Packages
CMOS 2048 × 9 Asynchronous FIFO
FUNCTIONAL DESCRIPTION
The LH540203 is a FIFO (First-In, First-Out) memory
device, based on fully-static CMOS dual-port SRAMtech-
nology, capable of storing up to 2048 nine-bit words. It
follows the industry-standard architecture and package
pinouts for nine-bit asynchronous FIFOs. Each nine-bit
LH540203 word may consist of a standard eight-bit byte,
together with a parity bit or a block-marking/framing bit.
The input and output ports operate entirely inde-
pendently of each other, unless the LH540203 becomes
either totally full or else totally empty. Data flow at a port
is initiated by asserting either of two asynchronous, as-
sertive-LOW control inputs: Write (W) for data entry at the
input port, or Read (R) for data retrieval at the output port.
Full, Half-Full, and Empty status flags monitor the
extent to which the internal memory has been filled. The
system may make use of these status outputs to avoid
the risk of data loss, which otherwise might occur either
by attempting to write additional words into an already-full
LH540203, or by attempting to read additional words from
an already-empty LH540203. When an LH540203 is
operating in a depth-cascaded configuration, the Half-Full
Flag is not available.
32-PIN PLCC
TOP VIEW
4 3 2 1 32 31 30
D₂
5
D₁
6
D₀
7
XI 8
29 D₆
28 D₇
27 NC
26 FL/RT
FF 9
25 RS
Q₀ 10
24 EF
Q₁ 11
23 XO/HF
NC 12
22 Q₇
Q₂ 13
21 Q₆
14 15 16 17 18 19 20
NOTE: * = No external electrical connections are allowed.
540203-3D
Figure 2. Pin Connections for PLCC Package
* This is a final data sheet; except that all references to the SOJ package have Advance Information status.
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