LH538700A Datasheet, PDF (1/6 Pages) Sharp Electrionic Components – CMOS 8M (1M x 8) MROM

LH538700A
PRELIMINARY
CMOS 8M (1M × 8) MROM
FEATURES
• 1,048,576 words × 8 bit organization
• Access time: 100 ns (MAX.)
• Power consumption:
Operating: 550 mW (MAX.)
Standby: 550 µW (MAX.)
• Static operation
• TTL compatible I/O
• Three-state outputs
• Single +5 V power supply
• Packages:
32-pin, 600-mil DIP
32-pin, 525-mil SOP
32-pin, 400-mil TSOP (Type II)
DESCRIPTION
The LH538700A is an 8M-bit mask-programmable
ROM organized as 1,048,576 × 8 bits. It is fabricated
using silicon-gate CMOS process technology.
PIN CONNECTIONS
32-PIN DIP
32-PIN SOP
TOP VIEW
A₁₉
1
A₁₆ 2
A₁₅ 3
A₁₂ 4
A₇ 5
A₆ 6
A₅ 7
A₄ 8
A₃ 9
A₂ 10
A₁ 11
A₀ 12
D₀ 13
D₁ 14
D₂ 15
GND 16
32 V_CC
31 A₁₈
30 A₁₇
29 A₁₄
28 A₁₃
27 A₈
26 A₉
25 A₁₁
24 OE
23 A₁₀
22 CE
21 D₇
20 D₆
19 D₅
18 D₄
17 D₃
538700A-1
Figure 1. Pin Connections for DIP and
SOP Packages
32-PIN TSOP (Type II)
TOP VIEW
A₁₉
1
A₁₆ 2
A₁₅ 3
A₁₂ 4
A₇ 5
A₆ 6
A₅ 7
A₄ 8
A₃ 9
A₂ 10
A₁ 11
A₀ 12
D₀ 13
D₁ 14
D₂ 15
GND 16
32 V_CC
31 A₁₈
30 A₁₇
29 A₁₄
28 A₁₃
27 A₈
26 ^A9
25 A11
24 OE
23 A₁₀
22 CE
21 D₇
20 D₆
19 D₅
18 D₄
17 D₃
NOTE: Reverse bend available on request.
538700A-2
Figure 2. Pin Connections for TSOP Package
1