LH5324500 Datasheet, PDF (1/7 Pages) Sharp Electrionic Components – CMOS 24M (3M x 8/1.5M x 16) MROM

LH5324500
CMOS 24M (3M × 8/1.5M × 16) MROM
FEATURES
• 3,145,728 words × 8 bit organization
(Byte mode)
1,572,864 words × 16 bit organization
(Word mode)
• Access time: 150 ns (MAX.)
• Power consumption:
Operating: 357.5 mW (MAX.)
Standby: 550 µW (MAX.)
• Static operation
• TTL compatible I/O
• Three-state outputs
• Single +5 V power supply
• Package: 44-pin, 600-mil SOP
DESCRIPTION
The LH5324500 is a 24M-bit mask-programmable
ROM organized as 3,145,728 × 8 bits (Byte mode) or
1,572,864 × 16 bits (Word mode) that can be selected
by a BYTE input pin. It is fabricated using silicon-gate
CMOS process technology.
PIN CONNECTIONS
44-PIN SOP
NC 1
A₁₈ 2
A₁₇ 3
A₇ 4
A₆ 5
A₅ 6
A₄ 7
A₃ 8
A₂ 9
A₁ 10
A₀ 11
CE 12
GND 13
OE 14
D₀ 15
D₈ 16
D₁ 17
D₉ 18
D₂ 19
D₁₀ 20
D₃ 21
D₁₁ 22
TOP VIEW
44 A₂₀
43 A₁₉
42 A₈
41 A₉
40 A₁₀
39 A₁₁
38 A₁₂
37 A₁₃
36 A₁₄
35 A₁₅
34 A₁₆
33 BYTE
32 GND
31 D₁₅/A_-1 (LSB)
30 D₇
29 D₁₄
28 D₆
27 D₁₃
26 D₅
25 D₁₂
24 D₄
23 V_CC
5324500-1
Figure 1. Pin Connections for SOP Package
1