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| LH531024 Datasheet, PDF (1/7 Pages) Sharp Electrionic Components – CMOS 1M (64K x 16) MROM | |||
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LH531024
CMOS 1M (64K Ã 16) MROM
FEATURES
⢠65,536 words à 16 bit organization
⢠Access time: 100 ns (MAX.)
⢠Power consumption:
Operating: 412.5 mW (MAX.)
Standby: 550 µW (MAX.)
⢠Static operation
⢠TTL compatible I/O
⢠Three-state outputs
⢠Single +5 V power supply
⢠JEDEC standard EPROM pinout (DIP)
⢠Packages:
40-pin, 600-mil DIP
40-pin, 525-mil SOP
44-pin, 650-mil QFJ (PLCC)
DESCRIPTION
The LH531024 is a mask-programmable ROM
organized as 65,536 Ã 16 bits. It is fabricated using
silicon-gate CMOS process technology.
PIN CONNECTIONS
40-PIN DIP
40-PIN SOP
TOP VIEW
NC 1
CE 2
D15
3
D14
4
D13
5
D12
6
D11
7
D10
8
D9
9
D8 10
GND 11
D7 12
D6 13
D5 14
D4 15
D3 16
D2 17
D1 18
D0 19
OE 20
40 VCC
39 NC
38 NC
37 A15
36 A14
35 A13
34 A12
33 A11
32 A10
31 A9
30 GND
29 A8
28 A7
27 A6
26 A5
25 A4
24 A3
23 A2
22 A1
21 A0
531024-1
Figure 1. Pin Connections for DIP and
SOP Packages
44-PIN PLCC
TOP VIEW
D12
D11
D10
D9
D8
GND
NC
D7
D6
D5
D4
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
531024-2
Figure 2. Pin Connections for QFJ
(PLCC) Package
1
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