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LH530800A Datasheet, PDF (1/6 Pages) Sharp Electrionic Components – CMOS 1M (128K x 8) MROM
LH530800A
CMOS 1M (128K × 8) MROM
FEATURES
• 131,072 words × 8 bit organization
• Access time: 150 ns (MAX.)
• Power consumption:
Operating: 192.5 mW (MAX.)
Standby: 550 µW (MAX.)
• Static operation
• TTL compatible I/O
• Three-state outputs
• Single +5 V power supply
• Packages:
32-pin, 600-mil DIP
32-pin, 525-mil SOP
32-pin, 450-mil QFJ (PLCC)
• JEDEC standard EPROM pinout (DIP)
DESCRIPTION
The LH530800A is a mask-programmable ROM
organized as 131,072 × 8 bits (1,048,576 bits). It is fab-
ricated using silicon-gate CMOS process technology.
PIN CONNECTIONS
32-PIN DIP
32-PIN SOP
TOP VIEW
NC 1
A16 2
A15 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
D0 13
D1 14
D2 15
GND 16
32 Vcc
31 NC
30 NC
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE/OE
23 A10
22 CE
21 D7
20 D6
19 D5
18 D4
17 D3
530800A-1
Figure 1. Pin Connections for DIP and
SOP Packages
32-PIN QFJ
TOP VIEW
4 3 2 1 32 31 30
A7 5
29 A14
A6 6
28 A13
A5 7
27 A8
A4 8
26 A9
A3 9
25 A11
A2 10
24 OE/OE
A1 11
A0 12
23 A10
22 CE
D0 13
21 D7
14 15 16 17 18 19 20
530800A-7
Figure 2. Pin Connections for QFJ
(PLCC) Package
1
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