LH52258A Datasheet, PDF (1/9 Pages) Sharp Electrionic Components – CMOS 32K x 8 Static RAM

LH52258A
CMOS 32K × 8 Static RAM
FEATURES
• Fast Access Times: 20/25 ns
• Low-Power Standby when Deselected
• TTL Compatible I/O
• 5 V ± 10% Supply
• Fully-Static Operation
• JEDEC Standard Pinout
• Packages:
28-Pin, 300-mil DIP
28-Pin, 300-mil SOJ
FUNCTIONAL DESCRIPTION
The LH52258A is a high-speed 262,144 bit static RAM
organized as 32K × 8. A fast, efficient design is obtained
with a CMOS periphery and a matrix constructed with
polysilicon load memory cells.
This RAM is fully static in operation. The Chip Enable
(E) control permits Read and Write operations when
active (LOW) or places the RAM in a low-power standby
mode when inactive (HIGH). Standby power (ISB1) drops
to its lowest level if E is raised to within 0.2 V of VCC.
Write cycles occur when both Chip Enable (E) and
Write Enable (W) are LOW. Data is transferred from the
DQ pins to the memory location specified by the 15
address lines. The proper use of the Output Enable
control (G) can prevent bus contention.
When E is LOW and W is HIGH, a static Read will
occur at the memory location specified by the address
lines. G must be brought LOW to enable the outputs.
Since the device is fully static in operation, new Read
cycles can be performed by simply changing the address.
High-frequency design techniques should be em-
ployed to obtain the best performance from this device.
Solid, low-impedance power and ground planes, with
high-frequency decoupling capacitors, are recom-
mended. Series termination of the inputs should be con-
sidered when transmission line effects occur.
PIN CONNECTIONS
28-PIN DIP
28-PIN SOJ
A₁₄
1
A₁₂
2
A₇ 3
A₆ 4
A₅
5
A₄
6
A₃
7
A₂
8
A₁ 9
A₀ 10
DQ₀ 11
DQ₁ 12
DQ₂ 13
V_SS 14
TOP VIEW
28 V_CC
27 _W
26 A₁₃
25 A₈
24 A₉
23 A₁₁
22 G
21 A₁₀
20 E
19 _DQ7
18 DQ₆
17 _DQ5
16 DQ₄
15 DQ₃
52258A-1D
Figure 1. Pin Connections for DIP and
SOJ Packages
1