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| LH52256C Datasheet, PDF (1/11 Pages) Sharp Electrionic Components – CMOS 256K (32K x 8) Static RAM | |||
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LH52256C/CH
CMOS 256K (32K Ã 8) Static RAM
FEATURES
⢠32,768 à 8 bit organization
⢠Access time: 70 ns (MAX.)
⢠Supply current:
Operating: 45 mA (MAX.)
10 mA (MAX.) (tRC, tWC = 1 µs)
Standby: 40 µA (MAX.)
⢠Data retention current: 1.0 µA (MAX.)
(VCCDR = 3 V, TA = 25°C)
⢠Wide operating voltage range:
4.5 V ± 5.5 V
⢠Operating temperature:
Commerical temperature 0°C to +70°C
Industrial temperature -40° to +85°C
⢠Fully-static operation
⢠Three-state outputs
⢠Not designed or rated as radiation
hardened
⢠Package:
28-pin, 600-mil DIP
28-pin, 450-mil SOP
28-pin, 300-mil SK-DIP
28-pin, 8 Ã 3 mm2 TSOP (Type I)
⢠N-type bulk silicon
DESCRIPTION
The LH52256C is a Static RAM organized as
32,768 Ã 8 bits which provides low-power standby
mode. It is fabricated using silicon-gate CMOS process
technology.
PIN CONNECTIONS
28-PIN DIP
28-PIN SK-DIP
28-PIN SOP
A14
1
A12
2
A7
3
A6 4
A5 5
A4 6
A3 7
A2
8
A1 9
A0 10
I/O1 11
I/O2 12
I/O3 13
GND 14
TOP VIEW
28 VCC
27 WE
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 I/O8
18 I/O7
17 I/O6
16 I/O5
15 I/O4
Figure 1. Pin Connections
52256C-1
28-PIN TSOP (Type I)
OE 1
A11
2
A9
3
A8
4
A13
5
WE 6
VCC
7
A14
8
A12
9
A7 10
A6 11
A5 12
A4 13
A3 14
28 A10
27 CE
26 I/O8
25 I/O7
24 I/O6
23 I/O5
22 I/O4
21 GND
20 I/O3
19 I/O2
18 I/O1
17 A0
16 A1
15 A2
NOTE: Reverse bend available on request.
52256C-8
Figure 2. TSOP (Type I) Pin Connections
1
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