LH521028A Datasheet, PDF (1/15 Pages) Sharp Electrionic Components – CMOS 64K x 18 Static RAM

LH521028A
CMOS 64K × 18 Static RAM
FEATURES
• Fast Access Times: 15/17/20/25/35 ns
• Wide Word (18-Bits) for:
– Improved Performance
– Reduced Component Count
– Nine-bit Byte for Parity
• Transparent Address Latch
• Reduced Loading on Address Bus
• Low-Power Stand-by Mode when
Deselected
• TTL Compatible I/O
• 5 V ± 10% Supply
• 2 V Data Retention
• JEDEC Standard Pinout
• Package: 52-Pin PLCC
FUNCTIONAL DESCRIPTION
The LH521028 is a high-speed 1,179,648-bit CMOS
SRAM organized as 64K × 18. A fast, efficient design is
obtained with a CMOS periphery and a matrix con-
structed with polysilicon load memory cells. The
LH521028 is available in a compact 52-Pin PLCC, which
along with the six pairs of supply terminals, provide for
reliable operation.
The control signals include Write Enable (W), Chip
Enable (E), High and Low Byte Select (SL and SH), Output
Enable (G) and Address Latch Enable (ALE). The wide
word provides for reduced component count, improved
density, reduced Address bus loading and improved per-
formance. The wide word also allows for byte-parity with
no additional RAM required.
This RAM is fully static in operation. The Chip Enable
(E) control permits Read and Write operations when
active (LOW) or places the RAM in a low-power standby
mode when inactive (HIGH).The Byte-select controls, SH
and SL, are also used to enable or disable Read and Write
operations on the high and the low bytes. The Address
Latches are transparent when ALE is HIGH (for applica-
tions not requiring a latch), and are latched when ALE is
LOW. The Address Latches and the wide word help to
eliminate the need for external Address bus buffers and/or
latches.
Write cycles occur when Chip Enable (E), SH and/or
SL, and Write Enable (W) are LOW. The Byte-select
signals can be used for Byte-write operations by disabling
the other byte during the Write operation. Data is trans-
ferred from the DQ pins to the memory location specified
by the 16 address lines. The proper use of the Output
Enable control (G) can prevent bus contention.
When E and either S_H or S_L are LOW and W is HIGH,
a static Read will occur at the memory location specified
by the address lines. G must be brought LOW to enable
the outputs. Since the device is fully static in operation,
new Read cycles can be performed by simply changing
the address with ALE HIGH.
PIN CONNECTIONS
52-PIN PLCC
TOP VIEW
DQ₉
DQ₁₀
V_CC
V_SS
DQ₁₁
DQ₁₂
DQ₁₃
DQ₁₄
V_SS
V_CC
DQ₁₅
DQ₁₆
DQ₁₇
7 6 5 4 3 2 1 52 51 50 49 48 47
8
46
9
45
10
44
11
43
12
42
13
41
14
40
15
39
16
38
17
37
18
36
19
35
20
34
21 22 23 24 25 26 27 28 29 30 31 32 33
DQ₈
DQ₇
DQ₆
V_CC
V_SS
DQ₅
DQ₄
DQ₃
DQ₂
V_SS
V_CC
DQ₁
DQ₀
521028-1D
Figure 1. Pin Connections for PLCC Package
1