LH28F008SC Datasheet, PDF (1/38 Pages) Sharp Electrionic Components – 8M (1M × 8) Flash Memory

LH28F008SC
8M (1M × 8) Flash Memory
FEATURES
• High-Density Symmetrically-Blocked
Architecture
– Sixteen 64K Erasable Blocks
• High-Performance
– 85 ns Read Access Time
• Enhanced Automated Suspend Options
– Byte Write Suspend to Read
– Block Erase Suspend to Byte Write
– Block Erase Suspend to Read
• Enhanced Data Protection Features
– Absolute Protection with V_PP = GND
– Flexible Block Locking
– Block Erase/Byte Write Lockout during
Power Transitions
• Extended Cycling Capability
– 100,000 Block Erase Cycles
– 1.6 Million Block Erase Cycles/Chip
• Low Power Management
– Deep Power-Down Mode
– Automatic Power Saving Mode Decreases
I_CC in Static Mode
• Automated Byte Write and Block Erase
– Command User Interface
– Status Register
• SmartVoltage Technology
– 3.3 V or 5 V V_CC
– 3.3 V, 5 V, or 12 V V_PP
• SRAM - Compatible Write Interface
• ETOX™ V Nonvolatile Flash Technology
• Industry - Standard Packaging
– 42-Pin, .67 mm × 8 mm² CSP Package
– 40-Pin, 1.2 mm × 10 mm × 20 mm
TSOP (Type I) Package
– 44-Pin, 600-mil, SOP Package
42-PIN CSP
TOP VIEW
1
A A₅
2
3
4
5
6
7
A₈ A₁₁ V_PP A₁₂ A₁₅ A₁₇
B A₄
A₇ A₁₀ V_CC A₁₃ NC A₁₈
C A₆ A₉ RP CE A₁₄ A₁₆ A₁₉
D A₃ DQ₁ NC V_CC DQ₄ DQ₇ NC
E A₂ A₀ DQ₃ GND DQ₆ OE NC
F A₁ DQ₀ DQ₂ GND DQ₅ RY/BY WE
28F008SC-20
Figure 1. CSP 42-Pin Configuration
40-PIN TSOP
TOP VIEW
A₁₉
1
A₁₈
2
A₁₇
3
A₁₆
4
A₁₅
5
A₁₄
6
A₁₃
7
A₁₂
8
CE ⁹
V_CC 10
V_PP 11
RP 12
A₁₁ 13
A₁₀ 14
A₉ 15
A₈ 16
A₇ 17
A₆ ¹⁸
A₅ 19
A₄ 20
40 NC
39 NC
38 WE
37 OE
36 RY/BY
35 DQ₇
34 DQ₆
33 DQ₅
32 DQ₄
31 V_CC
30 GND
29 GND
28 DQ₃
27 DQ₂
26 DQ₁
25 DQ₀
24 A₀
23 A₁
22 A₂
21 A₃
28F008SC-1
Figure 2. TSOP 40-Pin Configuration
1