SGM8093_15 Datasheet, PDF (9/18 Pages) SG Micro Corp – CMOS Operational Amplifiers

SGM8091/2/3/4
APPLICATION NOTES
Driving Capacitive Loads
The SGM8091/2/3/4 are optimized for bandwidth and speed,
not for driving capacitive loads. Output capacitance will
create a pole in the amplifier’s feedback path, leading to
excessive peaking and potential oscillation. If dealing with
load capacitance is a requirement of the application, the two
strategies to consider are (1) using a small resistor in series
with the amplifier’s output and the load capacitance and (2)
reducing the bandwidth of the amplifier’s feedback loop by
increasing the overall noise gain.
Figure 1 shows a unity gain follower using the series resistor
strategy. The resistor isolates the output from the
capacitance, and more importantly, creates a zero in the
feedback path that compensates for the pole created by the
output capacitance.
350MHz, Rail-to-Rail Output
CMOS Operational Amplifiers
For the high speed operational amplifier, soldering the part to
the board directly is strongly recommended. Try to keep the
high frequency big current loop area small to minimize the
EMI (electromagnetic interfacing).
+VS
10µF
0.1µF
+VS
10µF
0.1µF
Vn
SGM8091
Vp
Vn
VOUT
Vp
VOUT
SGM8091
10µF
SGM8091
VIN
RISO
VOUT
CLOAD
Figure 1. Series Resistor Isolating Capacitive Load
Power-Supply Bypassing and Layout
The SGM8091/2/3/4 operate from either a single +2.7V to
+5.5V supply or dual ±1.35V to ±2.75V supplies. For
single-supply operation, bypass the power supply +VS with a
0.1µF ceramic capacitor which should be placed close to the
+VS pin. For dual-supply operation, both the +VS and the -VS
supplies should be bypassed to ground with separate 0.1µF
ceramic capacitors. 2.2µF tantalum capacitor can be added
for better performance.
Good PC board layout techniques optimize performance by
decreasing the amount of stray capacitance at the op amp’s
inputs and output. To decrease stray capacitance, minimize
trace lengths and widths by placing external components as
close to the device as possible. Use surface-mount
components whenever possible.
-VS (GND)
0.1µF
-VS
Figure 2. Amplifier with Bypass Capacitors
Grounding
A ground plane layer is important for high speed circuit design.
The length of the current path speed currents in an inductive
ground return will create an unwanted voltage noise. Broad
ground plane areas will reduce the parasitic inductance.
Input-to-Output Coupling
To minimize capacitive coupling, the input and output signal
traces should not be parallel. This helps reduce unwanted
positive feedback.
SG Micro Corp
9
www.sg-micro.com