SGM6230 Datasheet, PDF (9/14 Pages) SG Micro Corp – Step-Down Converter

SGM6230
2A, 38V, 385kHz Step-Down Converter
APPLICATION INFORMATION
The RMS current in the input capacitor can be estimated
by:
I_RMS  I_LOAD 
V_OUT
V_IN
 _{}1
V_OUT
V_IN

The worst-case condition occurs at V_IN = 2V_OUT, where:
I_RMS(MAX)

I_LOAD
2
For simplification, choose the input capacitor whose RMS
current rating is greater than half of the maximum load
current.
In the case of ceramic capacitors, the impedance at the
switching frequency is dominated by the capacitance.
The output voltage ripple is mainly caused by the
capacitance. For simplification, the output voltage ripple
can be estimated by:
ΔV_OUT

V_OUT
8  f_S2  L  C_OUT
 _{}1
V_OUT
V_IN

In the case of tantalum or electrolytic capacitors, the ESR
dominates the impedance at the switching frequency. For
simplification, the output ripple can be approximated to:
ΔV_OUT

V_OUT
f_S  L

¹

V_OUT
V_IN
 ^{ RESR}
The input capacitor can be electrolytic, tantalum or
ceramic. When using electrolytic or tantalum capacitors,
a small, high quality ceramic capacitor, i.e. 0.1µF, should
be placed as close to the IC as possible. When using
ceramic capacitors, make sure that they have enough
capacitance to provide sufficient charge to prevent
excessive voltage ripple at input. The input voltage ripple
caused by capacitance can be estimated by:
ΔV_IN

I_LOAD
f_S  C_IN

V_OUT
V_IN
 _{}1
V_OUT
V_IN

C_IN is the input capacitance value.
Output Capacitor
The output capacitor (C_OUT) is required to maintain the
DC output voltage. Ceramic, tantalum, or low ESR
electrolytic capacitors are recommended.
The characteristics of the output capacitor also affect the
stability of the regulation system. The SGM6230 can be
optimized for a wide range of capacitance and ESR
values.
Compensation Components
SGM6230 employs current mode control for easy
compensation and fast transient response. The system
stability and transient response are controlled through the
COMP pin. COMP pin is the output of the internal
transconductance error amplifier. A serial capacitor and
resistor combination sets a pole-zero combination to control
the characteristics of the control system.
The DC gain of the voltage feedback loop is given by:
A _VDC
 R_LOAD
 G_CS
 A _EA

V_FB
V_OUT
Low ESR capacitors are preferred to keep the output
voltage ripple low. The output voltage ripple can be
estimated by:
Where A_EA is the error amplifier voltage gain, 10000V/V,
G_CS is the current sense transconductance, 6.2A/V, and
R_LOAD is the load resistor value.
ΔV_OUT

V_OUT
f_S  L
 _{}1
V_OUT
V_IN
 ^ ^RESR

8  f_S
1
 C_OUT

Where L is the inductor value, C_OUT is the output
capacitance value, and R_ESR is the equivalent series
resistance (ESR) value of the output capacitor.
The system has two poles of importance. One is due to
the compensation capacitor (C3) and the output resistor
of error amplifier, and the other is due to the output
capacitor and the load resistor. These poles are located
at:
f_P1

G _EA
2π  C3  A _EA
f_P2

1
2π  C_OUT
 R_LOAD
SG Micro Corp
9
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