SGM324_15 Datasheet, PDF (7/17 Pages) SG Micro Corp – CMOS Operational Amplifiers

SGM321/SGM358/SGM324
APPLICATION NOTES
Driving Capacitive Loads
The SGM321/SGM358/SGM324 can directly drive 250pF in
unity-gain without oscillation. The unity-gain follower (buffer) is
the most sensitive configuration to capacitive loading. Direct
capacitive loading reduces the phase margin of amplifiers and
this results in ringing or even oscillation. Applications that require
greater capacitive driving capability should use an isolation
resistor between the output and the capacitive load like the
circuit in Figure 1. The isolation resistor RISO and the load
capacitor C_L form a zero to increase stability. The bigger the R_ISO
resistor value, the more stable VOUT will be. Note that this method
results in a loss of gain accuracy because R_ISO forms a voltage
divider with the RLOAD.
SGM321
V_IN
R_ISO
VOUT
C_L
Figure 1. Indirectly Driving Heavy Capacitive Load
An improved circuit is shown in Figure 2. It provides DC accuracy
as well as AC stability. R_F provides the DC accuracy by
connecting the inverting signal with the output. CF and RIso serve
to counteract the loss of phase margin by feeding the high
frequency component of the output signal back to the amplifier’s
inverting input, thereby preserving phase margin in the overall
feedback loop.
1MHz, 60μA, Rail-to-Rail I/O
CMOS Operational Amplifiers
Power-Supply Bypassing and Layout
The SGM321/SGM358/SGM324 can operate from either a
single +2.1V to +5.5V supply or dual ±1.05V to ±2.75V
supplies. For single-supply operation, bypass the power
supply +VS with a 0.1µF ceramic capacitor which should be
placed close to the +V_S pin. For dual-supply operation, both
the +VS and the -VS supplies should be bypassed to ground
with separate 0.1µF ceramic capacitors. 2.2µF tantalum
capacitor can be added for better performance.
+VS
10µF
0.1µF
Vn
SGM321
Vp
Vn
VOUT
Vp
+VS
10µF
0.1µF
SGM321
VOUT
10µF
-VS (GND)
0.1µF
-VS
Figure 3. Amplifier with Bypass Capacitors
C_F
SGM321
V_IN
RISO
CL
RF
VOUT
RL
Figure 2. Indirectly Driving Heavy Capacitive Load with DC
Accuracy
For non-buffer configuration, there are two other ways to
increase the phase margin: (a) by increasing the amplifier’s gain
or (b) by placing a capacitor in parallel with the feedback resistor
to counteract the parasitic capacitance associated with inverting
node.
SG Micro Corp
7
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