100EL16TA-TD Datasheet, PDF (7/10 Pages) SEMTECH ELECTRONICS LTD. – Differential Receiver

SK10/100EL16TA-TD
HIGH-PER.ORMANCE PRODUCTS
AC Characteristics
PRELIMINARY
SK10/100EL16TA-TD AC Electrical Characteristics
(V_CC – V_EE = 3.0V to 5.5V)
TA = –40^oC
TA = 0^oC
TA = +25^oC
TA = +85^oC
Symbol Characteristic
Min Max Min Max Min Max Min Max Unit
f_max
t_PHL
t_PLH
tskew
t_r, t_f
V_CMR
Maximum Toggle
.requency⁴
Input to Output Delay
16TA
16TB
16TC
16TD
Duty Cycle Skew³
(DI..)
Output Rise Times
Q, Q* (20% to 80%)
16TA
16TB
16TC
16TD
Common MOde Range⁷
2.0
2.0
2.0
2.0
GHz
255 340 265 350 265 355 275 360
ps
260 300 270 310 275 320 285 335
ps
265 415 275 425 270 430 290 435
ps
270 375 275 380 285 385 285 390
ps
20
20
20
20
ps
115 190 115 195 115 195 120 205
ps
115 190 115 195 115 200 120 210
ps
90
235
90
235
90
235
90
235
ps
85
575
85
590
85
605
85
610
ps
V_EE + VCC – V_EE + VCC – V_EE + VCC – V_EE + VCC –
1.7
0.4
1.7
0.4
1.7
0.4
1.7
0.4
V
Notes:
1. 10EL circuits are designed to meet the DC specification shown in the table after thermal equilibrium has
been established. The circuit is in a test socket or mounted on a printed circuit board, and
transverse airflow greater than 500 lfpm is maintained.
2. 100K circuits are designed to meet the DC specification shown in the table where transverse airflow
greater than 500 lfpm is maintained.
3. Duty cycle skew is the difference between T_PLH and T_PHL propagation delay through a device.
4. F_MAX guaranteed for functionality only. See Figure 5 for typical output swing. VOL and VOH are
guaranteed at DC only.
5. Voltages referenced to VCC = 0V.
6. Minimum input swing for which parameters are guaranteed. The device has a DC gain of ~40.
7. CMR range is referenced to the most positive side of the differential input signal. Normal operation is
obtained if the high level falls within the specified range and the peak-to-peak voltage lies between
VPP_(min) and 1V. The lower end of the CMR range varies 1:1 with VEE and is equal to VEE + 1.7V.
8. VO_P-P is obtained as follows: Voltages of Q and Q* outputs with respect to VCC are measured. The
absolute difference between a high and a low state is equal to VO_pp.
9. For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specifications Data
Sheet.
10. For part ordering description, see HPP Part Ordering Information Data Sheet.
Revision 1/February 12, 2001
7
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