SC1211_03 Datasheet, PDF(9/11 Page) Semtech Corporation – High Speed, Combi-SenseTM Synchronous MOSFET Driver

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

SC1211_03 Datasheet, PDF (9/11 Pages) Semtech Corporation – High Speed, Combi-SenseTM Synchronous MOSFET Driver

◁

SC1211

POWER MANAGEMENT

Applications Information (Cont.)

VIN

Refer to Semtech SC2643VX Combi-SenseTM Current

Mode Controller about the details of the Combi-Sense

technique.

Qcst

VPN

DRN

Qcsb

PGND

SC1211

Rcs

Ccs

Inductor C urrent Signal

Vout

+ Co

The above circuit shows the concept of Combi-SenseTM

technique. An internal totem pole (Qcst, Qcsb) generates

a VPN (Virtual Phase Node) signal. This VPN follows the

DRN (or the Power Phase Node) with the same timing. A

RC network (Rcs and Ccs) is connected between VPN

and Vout. During Q1 turn-on, Qcst turns on as well. The

voltage drop across Q1 and Lo charges Ccs. During Q2

turn-on, Qcsb turns on as well. The voltage drop across

Q2 and Lo discharges Ccs. Both voltage drops are pro-

portional to the inductor current and a resistance equal

to FETâs Rdson plus ESR of the inductor. If the time con-

stant Rcs x Ccs is close to the Lo/Ro of the inductor,

where Ro is given by

Ro = Rinductor + Rdson_ hs * D + Rdson_ls * (1 - D)

the signal developed across Ccs will be proportional to

the inductor current, where Ro is the equivalent current

sensing resistance. In the above equation, Rinductor is

ESR of the inductor, Rdson_hs and Rdson_ls are the top

and bottom FETâs Rdson, and D is the duty cycle of the

converter.

Since a perfect timing match down to the nanosecond is

impossible, the VPN totem pole is held in tri-state during

the communtations of DRN in the SC1211. This avoids

errors and offset on the current detection which can be

significant since the timing mismatch is multiplied by the

input voltage. An optional capacitor between VPN and

DRN allows these two nodes to be AC coupled during

the tri-state window, hence yields a perfect timing match.

Optimized Gate Drive Voltage

With the supply voltage in between 9V to 16V, an inter-

nal LDO is designed with the SC1211 to bring the volt-

age to a lower level for gate drive. An external Ceramic

capacitor(1uF to 4.7uF) connected in between Vreg to

ground is needed to support the LDO. The LDO output is

connected to low gate drive internally, and has to be

connected to high gate drive through an external boot-

strap circuit. The LDO output voltage is set at 8.5V. The

manufacture data and bench tested results show that,

for low Rdson FETs run at applied load current, the opti-

mum gate drive voltage is around 8.5V, where the total

power losses of power FETs, including conduction loss

and switching loss, are minimized.

Thermal Shut Down

The SC1211 will shut down by pulling both driver out-

puts low if its junction temperature, Tj, exceeds 155Â°C.

COMPONENT SELECTION

Switching Frequency, Inductor and MOSFETs

The SC1211 is capable of providing up to 3.5A peak

drive current, and operating up to 1.5MHz PWM frequency

without causing thermal stress on the driver. The selec-

tion of switching frequency, together with inductor and

FETs is a trade-off between the cost, size, and thermal

management of a multi-phase voltage regulator. In mod-

ern microprocessor applications, these parameters could

be in the range of:

Switching Frequency

Inductor Value

FETs

100kHz to 500kHz per phase

0.2uH to 2uH

4m-ohm to 20m-ohm Rdson

20nC to 100nC total gate charge

Bootstrap Circuit

The SC1211 uses an external bootstrap circuit to pro-

vide a voltage for the top FET drive. This voltage, refer-

ring to the Phase Node, is held up by a bootstrap capaci-

www.semtech.com

▷