SC1182 Datasheet, PDF (8/12 Pages) Semtech Corporation – PROGRAMMABLE SYNCHRONOUS DC/DC CONVERTER, DUAL LOW DROPOUT REGULATOR CONTROLLER

August 25, 1998
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1182/3
LAYOUT GUIDELINES
Careful attention to layout requirements are necessary
for successful implementation of the SC1182/3 PWM
controller. High currents switching at 200kHz are pre-
sent in the application and their effect on ground plane
voltage differentials must be understood and mini-
mized.
1). The high power parts of the circuit should be laid
out first. A ground plane should be used, the number
and position of ground plane interruptions should be
such as to not unnecessarily compromise ground plane
integrity. Isolated or semi-isolated areas of the ground
plane may be deliberately introduced to constrain
ground currents to particular areas, for example the
input capacitor and bottom FET ground.
2). The loop formed by the Input Capacitor(s) (Cin), the
Top FET (Q1) and the Bottom FET (Q2) must be kept
as small as possible. This loop contains all the high
current, fast transition switching. Connections should
be as wide and as short as possible to minimize loop
inductance. Minimizing this loop area will a) reduce
EMI, b) lower ground injection currents, resulting in
electrically “cleaner” grounds for the rest of the system
and c) minimize source ringing, resulting in more reli-
able gate switching signals.
3). The connection between the junction of Q1, Q2 and
the output inductor should be a wide trace or copper
region. It should be as short as practical. Since this
connection has fast voltage transitions, keeping this
connection short will minimize EMI. The connection
between the output inductor and the sense resistor
should be a wide trace or copper area, there are no
fast voltage or current transitions in this connection
and length is not so important, however adding unnec-
essary impedance will reduce efficiency.
12V IN
5V
10
1 _AGND
GATE2 ²⁴
2 _GATE1
LDVO ²³
3 _LDOS1
VID0 ²²
0.1uF
4 _LDOS2
5 _VCC
VID1 ²¹
VID2 ²⁰
6 _OVP
VID3 ¹⁹
0.1uF ⁷ PWRGOOD
VID4 ¹⁸
8 _CS-
VO SENSE ¹⁷
9
CS+
16
EN
10 _PGNDH
BSTH ¹⁵
11 _DH
BSTL ¹⁴
12 _PGNDL
DL ¹³
SC1182/3
5V
+
Cin Lin
RA1
Q3
RB1
+
Cout Lin1
RA2
Q4
RB2
+
Cout Lin2
Layout diagram for the SC1182/3
Q1
Cin ₊
1.00k
2.32k
5mOhm
Vout
4uH
Q2
+
Cout
Heavy lines indicate
Vo Lin1
high current paths.
For SC1182, RA1, RA2, RB1 and RB2
are not required. LDOS1 connects to
Vo Lin1, LDOS2 connects to Vo Lin2
Vo Lin2
© 1998 SEMTECH CORP.
8
652 MITCHELL ROAD NEWBURY PARK CA 91320