SC1210 Datasheet, PDF (7/9 Pages) Semtech Corporation – High Speed, 12 V, Synchronous Power MOSFET Driver

SC1210
POWER MANAGEMENT
Applications Information
THEORY OF OPERATION
or heavy load conditions. At light load, it could force the
converter to sink current. Upon turn-off of the top FET,
The SC1210 is a high speed, dual output driver designed the reversed inductor current has to be freewheeling
to drive top and bottom MOSFETs in a synchronous Buck through the body diode of the top FET instead of the
converter. It features adaptive delay for shoot-through bottom FET. As a result, the phase node voltage remains
protection, VID-on-Fly operation, and internal LDO for op- high. The SC1210 incorporates the ability by pulling the
timum gate drive voltage. These drivers combined with bottom gate to high internally, which over rides the adap-
variety of Semtech PWM controllers form multi-phase tive circuit and turns the bottom FET on. The delay time
voltage regulators for advanced microprocessors.
from the PWM falling egde to the bottom gate turn-on is
set at 200ns typically.
UVLO
Optimized Gate Drive Voltage
A supply voltage has to be applied to VIN pin of the
SC1210. The top and bottom gates are held low until With the supply voltage in between 9V to 16V, an inter-
VIN exceeds UVLO threshold of the driver. Then the top nal LDO is designed with the SC1210 to bring the volt-
gate remains low and the bottom gate is pulled high to age to a lower level for gate drive. An external Ceramic
turn on the bottom FET.
capacitor(1uF to 4.7uF) connected in between Vreg to
ground is needed to decouple the LDO. The LDO output
Gate Transition and Shoot Through Protection powers up the low gate driver, and the high gate drive is
powered by the external bootstrap circuit. The LDO out-
Refer to the timing diagrams section, the rising edge of put voltage is set at 8.5V. The manufacture data and
the PWM input initiates the bottom FET turn-off and the bench tested results show that, for low Rdson FETs run
top FET turn-on. After a short propagation delay (tPDL_BG), at applied load current, the optimum gate drive voltage
the bottom gate begins to fall (tF_BG). An adaptive circuit is around 8.5V, where the total power losses of power
in the SC1210 monitors the bottom gate voltage to drop FETs, including conduction loss, switching loss, and the
below 1.4V. Then after a preset delay time (tPDH_TG) is gate drive loss, are minimized.
expired, the top gate turns on. The delay time is set to
be 20ns typically. This prevents the top FET from turning Thermal Shut Down
on until the bottom FET is off. During the transition, the
inductor current is freewheeling through the body diode The SC1210 will shut down by pulling both driver out-
of either bottom FET or top FET, upon the direction of puts low if its junction temperature, Tj, exceeds 155°C.
the inductor current. The phase node could be low
(ground) or high (VIN).
COMPONENT SELECTION
The falling edge of the PWM input controls the top FET
turn-off and the bottom FET turn-on. After a short propa- Bootstrap Circuit
gation delay (tPDL_TG), the top gate begins to fall (tF_TG).
As the inductor current is commutated from the top FET The SC1210 uses an external bootstrap circuit to pro-
to the body diode of the bottom FET, the phase node vide a voltage for the top FET drive. This voltage, refer-
begins to fall. The adaptive circuit in the SC1210 de- ring to the Phase Node, is held up by a bootstrap ca-
tects the phase node voltage. It holds the bottom FET pacitor.
off until the phase node voltage has dropped below 1.0V.
This prevents the top and bottom FETs from conducting Typically, it is recommended to use a 1uF ceramic ca-
simultaneously or shoot-through.
pacitor with 25V rating and a commonly available diode
IN4148 for the bootstrap circuit. In addition, a small
VID-on-Fly Operation
resistor may be added in between DRN of the SC1210
and the Phase Node. The resistor is used to allievate
Certain new processors have required to changing the the stress of the SC1210 from exposing to the negative
VID dynamically during the operation, or refered as VID- spike on the DRN pin. A negative spike could occur at
on-Fly operation. A VID-on-Fly can occur under light load
 2003 Semtech Corp.
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