SC1189 Datasheet, PDF (7/16 Pages) Semtech Corporation – Programmable synchronous DC/DC Converter, Dual LDO Controller

SC1189
POWER MANAGEMENT
Layout Guidelines
Careful attention to layout requirements are necessary for
successful implementation of the SC1189 PWM control-
ler. High currents switching at 200kHz are present in the
application and their effect on ground plane voltage differ-
entials must be understood and minimized.
1). The high power parts of the circuit should be laid out
first. A ground plane should be used, the number and
position of ground plane interruptions should be such as
to not unnecessarily compromise ground plane integrity.
Isolated or semi-isolated areas of the ground plane may
be deliberately introduced to constrain ground currents to
particular areas, for example the input capacitor and bot-
tom FET ground.
2). The loop formed by the Input Capacitor(s) (Cin), the Top
FET (Q1) and the Bottom FET (Q2) must be kept as small
as possible. This loop contains all the high current, fast
transition switching. Connections should be as wide and
as short as possible to minimize loop inductance. Mini-
mizing this loop area will a) reduce EMI, b) lower ground
injection currents, resulting in electrically “cleaner” grounds
for the rest of the system and c) minimize source ringing,
resulting in more reliable gate switching signals.
3). The connection between the junction of Q1, Q2 and
the output inductor should be a wide trace or copper re-
gion. It should be as short as practical. Since this connec-
tion has fast voltage transitions, keeping this connection
short will minimize EMI. The connection between the out-
put inductor and the sense resistor should be a wide trace
or copper area, there are no fast voltage or current transi-
tions in this connection and length is not so important,
however adding unnecessary impedance will reduce effi-
ciency.
12V IN
5V
10
0.1uF
1 _AGND
GATE2 ²⁴
2 _GATE1
LDOV ²³
3 _LDOS1
VID0 ²²
0.1uF
4 _LDOS2
5 _VCC
VID1 ²¹
VID2 ²⁰
6 _PWRGD
VID3 ¹⁹
7 _LDOEN
VID25MV ¹⁸
8 _CS-
VOSENSE ¹⁷
9 _CS+
EN ¹⁶
10 _PGNDH
BSTH ¹⁵
11 _DH
BSTL ¹⁴
12 _PGNDL
DL ¹³
SC1189
Q1
Cin ₊
1.00k
2.32k
5mOhm
Vout
L
Q2
+
Cout
3.3V
+
Cin Lin
Q3
+
Cout Lin1
Heavy lines indicate
Vo Lin1
high current paths.
Layout Diagram
SC1189
Q4
+
Cout Lin2
Vo Lin2
 2004 Semtech Corp.
7
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