SC488 Datasheet, PDF (6/24 Pages) Semtech Corporation – Complete DDR1/2/3 Memory Power Supply

POWER MANAGEMENT
Pin Configuration
SSCC4880 MLP24 Pin Out
PGND2 1
18 ^PGND1
VTTS ²
17 ^PGND1
VSSA ³
16 ILIM
T
TON ⁴
15 VDDP
REF ⁵
14 _VDDP
VCCA ⁶
13 _PGD
SC488
Ordering Information
Device⁽²⁾
SC488MLTRT
Package⁽¹⁾
MLPQ-24
Notes:
1) Only available in tape and reel packaging. A reel contains 3000 devices.
2) This product is fully WEEE and RoHS compliant.
Pin Description
Pin # Pin Name Pin Function
1
PGND2 Power ground for VTT output. Connect to thermal pad and ground plane.
2
VTTS Sense pin for VTT. Connect to VTT at the load.
3
VSSA Ground reference for analog circuitry. Connect to thermal pad.
4
TON
This pin is used to sense VBAT through a pull-up resistor, RTON, which sets the top MOSFET
on-time. Bypass this pin with a 1nF capacitor to VSSA.
5
REF
Reference output. An internal resistor divider from VDDQS sets this voltage to 50% VDDQ (nomi-
nal). Bypass this pin with a series 10Ω/1μF to VSSA.
6
VCCA Analog supply voltage input. Use a 10Ω/1μF RC filter from +5V to VSSA.
7
NC
No connect.
8
VDDQS Sense input for VDDQ. Used to set the on-time for the top MOSFET and also to set REF/VTT.
9
FB
Feedback select input for VDDQ. See FB Configuration Table.
10
VTTEN
Enable pin for VTT. Pull this pin low to disable VTT (REF remains present as long as VDDQ is
present).
Enable/Power Save input pin. Tie to ground to disable VDDQ. Tie to +5V to enable VDDQ and
11
EN/PSV activate PSAVE mode. Float to enable VDDQ and activate continous conduction mode. If floated,
bypass to VSSA with a 10nF capacitor.
12
NC
No connect.
13
PGD
Power good output for VDDQ. PGD is low if VDDQ is outside the power good thresholds. This
pin is an open drain NMOS output and requires an external pull-up resistor.
© 2006 Semtech Corp.
6
www.semtech.com