GS9091B Datasheet, PDF (53/73 Pages) Gennum Corporation – GenLINX II 270Mb/s Deserializer for SDI and DVB-ASI

3.10.2 DVB-ASI Mode
The internal FIFO is in DVB-ASI mode when the FIFO_EN pin is set HIGH, and the
FIFO_MODE[1:0] bits in the IOPROC_DISABLE register are configured to 01b. By
default, the FIFO_MODE[1:0] bits are set to 01b by the device whenever the DVB_ASI
pin is set HIGH (i.e. the device is in DVB-ASI mode); however, the FIFO_MODE[1:0] bits
may be programmed as required.
Figure 3-10 shows the input and output signals of the FIFO when it is configured for
DVB-ASI Mode.
8-bit MPEG Data
Internal
Application Interface
8-bit MPEG Data
WORDERR
SYNCOUT
FIFO
(DVB-ASI Mode)
WORDERR
SYNCOUT
WR_CLK
(PCLK gated with SYNCOUT)
Figure 3-10: FIFO in DVB-ASI Mode
FIFO_EMPTY
FIFO_FULL
RD_CLK
When operating in DVB-ASI mode, the GS9091B's FIFO can be used for clock rate
interchange operation. The extracted 8-bit MPEG packets will be written into the FIFO
at 27MHz based on the SYNCOUT signal from the internal DVB-ASI decoder block. The
SYNCOUT and WORDERR bits are also stored in the FIFO (see Section 3.7.2).
When SYNCOUT goes HIGH, K28.5 stuffing characters have been detected and no data
will be written into the FIFO.
Data is read out of the FIFO using the RD_CLK pin. In DVB-ASI mode, the RD_RESET pin
is not used.
Note: With the internal FIFO enabled in DVB-ASI mode, SYNCOUT will always be LOW
since the K28.5 sync characters are not stored in the FIFO.
GS9091B GenLINX® II 270Mb/s Deserializer for SDI
and DVB-ASI
Final Data Sheet
38910 - 3
February 2013
53 of 73
Proprietary & Confidential