SFC2309-200 Datasheet, PDF (5/10 Pages) Semtech Corporation – Flip Chip TVS Diode with T-Filter for Color LCD Interface Protection

SFC2309-200
PROTECTION PRODUCTS
Applications Information
Printed Circuit Board Finish
A uniform board finish is critical for good assembly
yield. Two finishes that provide uniform surface coat-
ings are immersion nickel gold and organic surface
protectant (OSP). A non-uniform finish such as hot air
solder leveling (HASL) can lead to mounting problems
and should be avoided.
Stencil Design
A properly designed stencil is key to achieving ad-
equate solder volume without compromising assembly
yields. A 0.100mmto 0.200mm thick, laser cut, electro-
polished stencil with 0.330mm apertures corners with
rounded corners is recommended.
Reflow Profile
The flip chip TVS can be assembled using standard
SMT reflow processes. As with any component, ther-
mal profiles at specific board locations can vary & must
be determined by the manufacturer. The flip chip TVS
peak reflow temperature is 230 ± 10 °C for a maxi-
mum time of 10 seconds. Time above eutectic tem-
perature (183 °C) should be 50 ± 10 seconds. During
reflow, the component self-aligns itself on the pad.
PRELIMINARY
Recommended NSMD Pad and Stencil Aperture
Solder Reflow Profile
Circuit Board Layout Recommendations for Suppres-
sion of ESD
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
z Place the TVS near the input terminals or connec-
tors to restrict transient coupling.
z Minimize the path length between the TVS and the
protected line.
z Minimize all conductive loops including power and
ground loops.
z The ESD transient return path to ground should be
kept as short as possible.
z Never run critical signals near board edges.
z Use ground planes whenever possible.
 2003 Semtech Corp.
5
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