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SC4608 Datasheet, PDF (5/19 Pages) Semtech Corporation – Low Input, MHz Operation, High Efficiency Synchronous Buck
POWER MANAGEMENT
Pin Configuration
TOP VIEW
SC4608
Ordering Information
Part Number
Device(1)
SC4608MLTRT(2)
MLP-16
SC4608EVB
Evaluation Board
Notes:
(1) Only available in tape and reel packaging. A reel
contains 3000 devices.
(2) Lead free product. This product is fully WEEE and
RoHS compliant.
(16 Pin MLP)
Pin Descriptions
Pin #
1
2
3
4
5
Pin Name
AVDD
ISET
COMP
FSET
EN
Pin Function
Power supply voltage for the analog section of the controller.
The ISET pin is used to limit current in the high side MOSFET. The SC4608 uses the
voltage across the VIN and ISET pins in order to set the current limit. The current limit
threshold is set by the value of an external resistor (R3 in the Typical Application Circuit
Diagram). Current limiting is performed by comparing the voltage drop across the sense
resistor with the voltage drop across the drain to source resistance of the high side
MOSFET during the MOSFET’s conduction period. The voltage drop across the drain to
source resistance of the high side MOSFET is obtained from the VIN and PHASE pin.
This is the output of the voltage error amplifier. The voltage at this output is inverted
internally and connected to the non-inverting input of the PWM comparator. A lead-lag
network from the COMP pin to the VSENSE pin compensates for the two pole LC filter
characteristics inherent to voltage mode control. The lead-lag network is required in order
to optimize the dynamic performance of the voltage mode control loop.
The FSET pin is used to sets the PWM oscillator frequency through an external timing
capacitor that is connected from the FSET pin to the GND pin. The SC4608 can be
operated in synchronous mode by placing a resistor in series between the timing capacitor
and ground. The other terminal of the timing capacitor will remain connected to the FSET
pin.
The oscillator frequency of the SC4608 is set by FSET when EN is pulled and held above
0.7 * AVDD. Its shutdown mode is invoked if EN is pulled and held below 0.3 * AVDD.
 2006 Semtech Corp.
5
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