SC1405 Datasheet, PDF (5/12 Pages) Semtech Corporation – HIGH SPEED SYNCHRONOUS POWER MOSFET SMART DRIVER

HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER
SC1405
August 31, 2000
PIN DESCRIPTION
Pin #
1
Pin Name
OVP_S
2 EN
3 GND
4 CO
5 S_MOD
6 DELAY_C
7 PRDY
8
V_CC
9 BG
10 PGND
11 DSPS_DR
12 DRN
13 TG
14 BST
Pin Function
Overvoltage protection sense. External scaling resistors required to set
protection threshold.
When high, this pin enables the internal circuitry of the device. When
low, TG, BG and PRDY are forced low and the supply current (5V) is
less than 10µA.
Logic GND.
TTL-level input signal to the MOSFET drivers.
When low, this signal forces BG to be low. When high, BG is not a
function of this signal.
Sets the additional propagation delay for BG going low to TG going high.
Total propagation delay= 20ns + 1ns/pF.
This pin indicates the status of 5V. When 5V is less than 4.4V(typ) this
output is driven low. When 5V is greater than or equals to 4.4V(typ) this
output is driven to 5V level. This output has a 10mA drive capability and
10µA sink capability.
+5V supply. A .22-1µF ceramic capacitor should be connected from 5V
to PGND very close to this pin.
Output drive for the synchronous MOSFET.
Power ground. Connect to the synchronous FET power ground.
Dynamic Set Point Switch Drive. TTL level output signal. When S_MOD
is high, this pin follows the BG driver pin voltage.
This pin connects to the junction of the switching and synchronous
MOSFET’s. This pin can be subjected to a -2V minimum relative to
PGND without affecting operation.
Output gate drive for the switching (high-side) MOSFET.
Bootstrap pin. A capacitor is connected between BST and DRN pins to
develop the floating bootstrap voltage for the high-side MOSFET. The
capacitor value is typically between 0.1µF and 1µF (ceramic).
NOTE:
(1) All logic level inputs and outputs are open collector TTL compatible.
PIN CONFIGURATION
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