EDGE6435 Datasheet, PDF (38/40 Pages) Semtech Corporation – Per-Pin Electronics Companion DAC

Edge6435/6436
TEST AND MEASUREMENT PRODUCTS
AC Characteristics (continued)
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
DAC_OUT Readback Time is the amount of time required for DAC_OUT to display a valid voltage for a
selected (and fully settled) DAC channel and only includes channel-to-channel switching time.
Measured from CLKIN using edge of update to specified accuracy.
Rank Transition Time is a measurement of the time required to change between Rank A and Rank B
latches and does not include DAC Output Settling time.
DAC Output Enable Time is measured after DACEN is transitioned from 0 to 1 from the rising edge of
the clock signal applied to CLKIN as the time required for the DAC output to change by 10%.
Voltage DAC output disable time is measured from the falling edge of DACEN as the amount of time
required for the DAC output to change from positive full-scale to 0.5V.
Current DAC Output Disable Time is measured from the falling edge of DACEN as the amount of time
required for the DAC output to change by 10%.
CLKIN
LOAD
C
CK24
TSU_LD THLD_LD
3C
TSU_STR THLD_STR
STORE
TSU_STR
16C
UPDATEA (Internal)
UPDATE _ _ _ _ _ _ _
2C
TSU_UPD THLD_UPD
TSU_UPD
RANK _ _ _ _ _ _ _ _
TSU_RNK
THLD_RNK TSU_RNK
THLD_RNK
Figure 21. Individual DAC Storing and DAC Updating (RESET* high)
SDIN
CKIN
Valid Data
A0
TSU_SDI
THLD_SDI
CK1
SDOUT
TO_SDOUT
Previous
A0
Valid Data
R2
TSU_SDI
THLD_SDI
CK24
A1
Figure 22. Shift Register Loading Timing Diagram
 2006 Semtech Corp. / Rev. 3, 8/25/06
38
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