SC2441A_09 Datasheet, PDF (35/37 Pages) Semtech Corporation – 1.8V to 20V Input 2-Phase Synchronous Step-down Controllers with Step-up Converter

SC2441A
POWER MANAGEMENT
Applications Information
73.323 ¹⁰⁰
50
( ) ^{20×log G} _vc(f) ^C(f)
0
PC Board Layout Issues
Circuit board layout is very important for the proper
operation of high frequency switching power converters.
A power ground plane is required to reduce ground
bounces. The followings are suggested for proper layout.
Power Stage
- 17.588 ₅₀
10
10
- 90.001 ⁹⁰
92
( ) ^{arg G} _vc(f)^×C(f)
180
×
p
94
1) Separate the power ground from the signal ground. In
100 1 ^.10³ 1 ^.10⁴ 1 ^.10⁵ 1 ^.10⁶ SC2441A the power ground PGND1 should be tied to
f
3´10⁵ _{the source terminal of lower MOSFETs. The signal ground}
AGND should be tied to the negative terminal of the
f
output capacitor (output return terminal).
2) Minimize the size of pulse current loop. Place the top
MOSFET, the bottom MOSFET and the input capacitors
close to each other with short and wide traces. In addition
to the aluminum energy storage capacitors, add multi-
layer ceramic (MLC) capacitors from the input to the power
ground to improve high frequency bypass.
- 94.713 ₉₆
10
10
100
1 ^.10³
1 ^.10⁴
1 ^.10⁵
1 ^.10⁶
f
3´10⁵
Figure 25. Bode plots of the loop response.
The resulting crossover frequency is about 49.2kHz with
phase margin 90^o.
If the circuit noise makes the converter jitter, a larger C₃
than the calculated value can be used. Effectively the
converter bandwidth is reduced to reject high frequency
noises. The final circuit should be checked for stability
under load transients at different line voltages. The load
transient also needs to be measured to ensure that the
output voltage is within the specification window.
3) Reduce high frequency voltage ringing. Widen and
shorten the drain and source traces of the MOSFETs to
reduce stray inductances. Add a small RC snubber if
necessary to reduce the high frequency ringing at the
phase node. Sometimes slowing down the gate drive
signal also helps in reducing the high frequency ringing at
the phase node.
4) Shorten the gate driver path. Integrity of the gate drive
(voltage level, leading and falling edges) is important for
circuit operation and efficiency. Short and wide gate drive
traces reduce trace inductances. Bond wire inductance
is about 2~3nH. If the length of the PCB trace from the
gate driver to the MOSFET gate is 1 inch, the trace
inductance will be about 25nH. If the gate drive current
is 2A with 10ns rise and falling times, the voltage drops
across the bond wire and the PCB trace will be 0.6V and
5V respectively. This may slow down the switching
transient of the MOSFETs. These inductances may also
ring with the gate capacitance.
5) Put the decoupling capacitor for the gate drive power
supplies (BST and VCC) close to the IC and power ground.
 2006 Semtech Corp.
35
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