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SC402B Datasheet, PDF (27/32 Pages) Semtech Corporation – 10A EcoSpeed® Integrated FET Regulator with Programmable LDO
SC402B
Applications Information (continued)
SC402B regulates to the valley of the ripple voltage at the
FB pin, a high ripple magnitude is undesirable as it signifi-
cantly impacts the output voltage regulation. As a result,
it is desirable to select a corner frequency for (R1// R2) x CC
to achieve enough, but not excessive, ripple magnitude
and phase margin. The component values for R1, R2, and
CC should be calculated using the following procedure.
Select CL (typical 10nF) and RL to match with L and DCR
time constant using the following equation.
RL
L
DCR u CL
Select CC by using the following equation.
CC
|
1
R1 // R2
u
3
2 u S u fsw
The resistor values (R1 and R2) in the voltage divider circuit
set the VOUT for the switcher. The typical value for CC is
from 10pF to 1nF.
The on-time pulse from the SC402B in the design example
is calculated to give a pseudo-fixed frequency of 300kHz.
Some frequency variation with line and load is expected.
This variation changes the output ripple voltage. Because
adaptive on-time converters regulate to the valley of the
output ripple, ½ of the output ripple appears as a DC regu-
lation error. For example, if the output ripple is 50mV with
VIN = 6 volts, then the measured DC output will be 25mV
above the comparator trip point. If the ripple increases to
80mV with VIN = 25V, then the measured DC output will be
40mV above the comparator trip. The best way to mini-
mize this effect is to minimize the output ripple.
The use of 1% feedback resistors may result in up to 1%
error. If tighter DC accuracy is required, 0.1% resistors
should be used.
The output inductor value may change with current. This
will change the output ripple and therefore will have a
minor effect on the DC output voltage. The output ESR
also affects the output ripple and thus has a minor effect
on the DC output voltage.
Dropout Performance
The output voltage adjustment range for continuous con-
duction operation is limited by the fixed 250ns (typical)
minimum off-time of the one-shot. When working with
low input voltages, the duty-factor limit must be calcu-
lated using worst-case values for on and off times.
The duty-factor limitation is shown by the next equation.
DUTY
TON(MIN)
T  T ON(MIN)
OFF(MAX)
The inductor resistance and MOSFET on-state voltage
drops must be included when performing worst-case
dropout duty-factor calculations.
Switching Frequency Variation
The switching frequency varies with load current as a
result of the power losses in the MOSFETs and DCR of the
inductor. For a conventional PWM constant-frequency
converter, as load increases the duty cycle also increases
slightly to compensate for IR and switching losses in the
MOSFETs and inductor. An adaptive on-time converter
must also compensate for the same losses by increasing
the effective duty cycle (more time is spent drawing
energy from VIN as losses increase). The on-time is essen-
tially constant for a given VOUT/VIN combination, to offset
the losses the off-time will tend to reduce slightly as load
increases. The net effect is that switching frequency
increases slightly with increasing load.
System DC Accuracy (VOUT Controller)
Three factors affect VOUT accuracy: the trip point of the FB
error comparator, the ripple voltage variation with line
and load, and the external resistor tolerance. The error
comparator offset is trimmed so that under static condi-
tions it trips when the feedback pin is 750mV, 1%.
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