GS2965 Datasheet, PDF (23/41 Pages) Gennum Corporation – Uses standard 27MHz crystal

Table 4-9: Bypass Modes
Bypass
HIGH
LOW
LOW
Autobypass
X
HIGH
LOW
Device Operation
Bypass Mode
Bypass Mode if the PLL has not
locked to a data rate
Power-up default. Normal
Operation, part always tries to
lock to the incoming data
stream.
Note that if BYPASS is HIGH, this will override the AUTOBYPASS functionality.
When the GS2965's PLL is not locked and BYPASS = LOW and AUTOBYPASS = LOW, the
serial digital output DDO/DDO will produce invalid data.
The AUTOBYPASS function will bypass unsupported (non-reclocked) SMPTE SDI signal
rates without producing bit errors: 143Mb/s, 177Mb/s, 360Mb/s, 540Mb/s.
4.13 DVB-ASI
The GS2965 also reclocks DVB-ASI signals at 270Mb/s. In auto mode, the device will
automatically lock to the incoming 270Mb/s signal. In manual mode, the SS[1:0] bits
must be set to 01 (270Mb/s) to ensure proper operation.
4.14 Output Mute and Data/Clock Output Selection
The DATA_MUTE register is provided to allow muting of the serial digital data output.
Setting DATA_MUTE = LOW will force the serial digital outputs DDO/DDO to mute
(statically latch HIGH) under all conditions and operating modes.
The DDO1_DISABLE register is provided to allow the second data/clock output to be
powered down.
When DDO1_DISABLE is set LOW, the serial digital clock outputs DDO1/RCO and
DDO1/RCO are muted and the driver is powered-down.
The DATA/CLOCK register is provided to allow the second output to emit a copy of the
reclocked serial data or the recovered clock.
Table 4-10: Configuration of GS2965 Output Drivers and Mute/Disable Pins
DATA_MUTE
1
1
0
0
DDO1_DISABLE
1
1
1
1
DATA/CLOCK
0
1
0
1
DDO0
DATA
DATA
MUTE
MUTE
DDO1/RCO
CLOCK
DATA
CLOCK
MUTE
GS2965 Multi-Rate SDI Reclocker with Equalization &
De-emphasis
Data Sheet
52462 - 4
July 2012
23 of 41
Proprietary & Confidential