SC1159 Datasheet, PDF (20/20 Pages) Semtech Corporation – Programmable Synchronous DC/DC Hysteretic Controller with VRM 8.5 VID Range

SC1159
POWER MANAGEMENT
Layout Guidelines (See pg. 1)
1. Locate R8 and C2 close to pins 6 and 7.
2. Locate C1 close to pins 5 and 7.
3. Components connected to IOUT, DROOP, OCP, VHYST,
VREFB, VSENSE, and SOFTST should be referenced to
AGND.
4. The bypass capacitors C5 and C10 should be placed
close to the IC and referenced to DRVGND.
5. Locate bootstrap capacitor C13 close to the IC.
6. Place bypass capacitor close to Drain of the top FET and
Source of the bottom FET to be effective.
7. Route HISENSE and LOSENSE close to each other to
minimize induced differential mode noise.
8. Bypass a high frequency disturbance with ceramic
capacitor at the point where HISENSE is connected to Vin.
9. Input bulk capacitors should placed as close as possible
to the power FETs because of the very high ripple current
flow in this pass.
10. If Schottky diode used in parallel with a synchronous
(bottom) FET, to achieve a greater efficiency at lower Vout
settings, it needs to be placed next to the aforementioned
FET in very close proximity.
11. Since the feedback path relies on the accurate sampling
of the output ripple voltage, the best results can be achieved
by connecting the AGND to the ground side of the bulk
output capacitors.
12. DRVGND pin should be tight to the main ground plane
utilizing very low impedance connection, e.g., multiple vias.
13. In order to prevent substrate glitching, a small (0.5A)
Schottky diode should be placed in close proximity to the
chip with the cathode connected to BOOTLO and anode
connected to DRVGND.
Outline Drawing - SO-28
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: [phone] FAX [phone]
 2002 Semtech Corp.
20
www.semtech.com