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SC2441 Datasheet, PDF (19/35 Pages) Semtech Corporation – Very Low Input Voltage 2-Phase Synchronous Step-down Controllers with Step-up Converter
SC2441
POWER MANAGEMENT
Applications Information (Cont.)
The conduction loss is then
Pbc=IQ2,rms2 Rds(on),
where R is the channel resistance of bottom MOSFET.
ds(on)
If the input voltage to output voltage ratio is high (e.g.
Vin=12V, Vo=1.5V), the duty ratio D will be small. Since the
bottom switch conducts with duty ratio (1-D), the
corresponding conduction losses can be quite high.
Due to non-overlapping conduction between the top and
the bottom MOSFET’s, the internal body diode or the
external Schottky diode across the drain and source
terminals always conducts prior to the turn on of the bottom
MOSFET. The bottom MOSFET switches on with only a diode
voltage between its drain and source terminals. The
switching loss
Pbs
=
1
2
(t
r
+ tf )(1+
δ
2
)Io
Vd
fs
is negligible due to near zero-voltage switching.
The gate loss is estimated as
Pbg
=
Rg
R gt
QgVcc fs.
The total bottom switch loss is then
Using low gate charge MOSFET’s reduces switching loss.
It is possible to trade driver IC losses for MOSFET
switching losses by adjusting the gate resistance. Lower
gate resistance results in higher gate driving current and
faster MOSFET switching. However the driver incurs
higher losses. Conversely higher gate drive resistance
limits the gate drive current, thus lowering the driver
dissipation. MOSFET switching loss is higher.
To prevent shoot-through between the top and the bottom
MOSFET’s during commutation, one MOSFET should be
completely turned off before the other is turned on. In the
SC2441 the top and the bottom gate drive pulses are made
non-overlapping. When not driving any load, the non-
overlapping commutation intervals from the top to the
bottom and from the bottom to the top gate drives are set
at 62ns and 74ns respectively. If MOSFET’s are driven from
the SC2441, the non-overlapping commutation times will
decrease due to finite gate-source voltage rise and fall times.
The gate-source voltage waveforms of the MOSFET’s should
not overlap above their respective thresholds when driven
from the SC2441. Use of low gate charge MOSFET’s reduces
transition times and the tendency of shoot-through. The
combined rise and fall times during both commutations
should be less than the preset non-overlapping intervals
Pb=Pbc+Pbs+Pbg.
Once the power losses Ploss for the top (Pt) and bottom (Pb)
MOSFET’s are known, thermal and package design at
component and system level should be done to verify that
the maximum die junction temperature (Tj,max, usually
125oC) is not exceeded under the worst-case conditions.
The equivalent thermal impedance from junction to
ambient (θja) should satisfy
θ ja
≤
Tj,max − Ta,max
Ploss
.
θja depends on the die to substrate bonding, packaging
material, the thermal contact surface, thermal compound
property, the available effective heat sink area and the air
flow condition (free or forced convection). Actual temperature
measurement of the prototype should be carried out to
verify the thermal design.
Integrated Power MOSFET Drivers
There are four internal MOSFET drivers in step-down
section of the SC2441 for driving all the MOSFET’s in a
dual-channel step-down converter.
Current Sensing (Combi-Sense)
Inductor current sensing is required for the current-mode
control. Although the inductor current can be sensed with
a precision resistor in series with the inductor, a novel
(US patent 6,441,597) lossless combi-sense technique
can also be used in the SC2441. This Semtech proprietary
technique has the following advantages
1) lossless current sensing
2) higher signal-to-noise ratio and
3) preventing thermal run-away.
The basic arrangement of the combi-sense is shown in
Figure 12.
In Figure 12 RL is the equivalent series resistance of the
output inductor. Rs and Cs form a RC network for inductor
current sensing. This branch is driven from a small totem
pole driver (Q3 and Q4) within the SC2441. The base
driving signals Vbe3 and Vbe4
 2005 Semtech Corp.
19
www.semtech.com