SC643 Datasheet, PDF (17/26 Pages) Semtech Corporation – Light Management Unit with 4 LDOs and SemPulse®Interface

SC643
SemPulse_® Interface
Introduction
SemPulse is a write-only single wire interface. It provides
access to up to 32 registers that control device functional-
ity. Two sets of pulse trains are transmitted to generate a
complete SemPulse command. The first pulse set is used
to set the desired address. After the bus is held high for
the address hold period, the next pulse set is used to write
the data value. After the data pulses are transmitted, the
bus is held high again for the data hold period to signify
the data write is complete. At this point the device latches
the data into the address that was selected by the first set
of pulses. See the SemPulse Timing Diagrams for descrip-
tions of all timing parameters.
Chip Enable/Disable
The device is enabled when the SemPulse interface pin
(SPIF) is pulled high for greater than t . If the SPIF pin is
SU
pulled low again for more than t , the device will be
SD
disabled.
Address Writes
The first set of pulses can range between 0 and 31 (or 1 to
32 rising edges) to set the desired address. After the
pulses are transmitted, the SPIF pin must be held high for
t to signal to the slave device that the address write is
HOLDA
finished. If the pulse count is between 0 and 31 and the
line is held high for t , the address is latched as the
HOLDA
destination for the data word. If the SPIF pin is not held
high for t , the slave device will continue to count
HOLDA
pulses. If the total exceeds 31 pulses, the write will be
ignored and the bus will reset after the next valid hold
time is detected. Note that if t exceeds its maximum
HOLDA
specification, the bus will reset. This means that the com-
munication is ignored and the bus resumes monitoring
the pin, expecting the next pulse set to be an address.
Data Writes
After the bus has been held high for the minimum address
hold period, the next set of pulses are used to write the
data value. The total number of pulses can range from 0
to 63 (or 1 to 64 rising edges) since there are a total of 6
register bits per register. Just like with the address write,
the data write is only accepted if the bus is held high for
t when the pulse train is completed. If the proper
HOLDD
hold time is not received, the interface will keep counting
pulses until the hold time is detected. If the total exceeds
63 pulses, the write will be ignored and the bus will reset
after the next valid hold time is detected. After the bus
has been held high for t , the bus will expect the next
HOLDD
pulse set to be an address write. Note that this is the same
effect as the bus reset that occurs when t exceeds its
HOLDA
maximum specification. For this reason, there is no
maximum limit on t — the bus simply waits for the
HOLDD
next valid address to be transmitted.
Multiple Writes
It is important to note that this single-wire interface
requires the address to be paired with its corresponding
data. If it is desired to write multiple times to the same
address, the address must always be re-transmitted prior
to the corresponding data. If it is only transmitted one
time and followed by multiple data transmissions, every
other block of data will be treated like a new address. The
result will be invalid data writes to incorrect addresses.
Note that multiple writes only need to be separated by
the minimum t_HOLDD for the slave to interpret them cor-
rectly. As long as t between the address pulse set and
HOLDA
the data pulse set is less than its maximum specification
but greater than its minimum, multiple pairs of address
and data pulse counts can be made with no detrimental
effects.
Standby Mode
Once data transfer is completed, the SPIF line must be
returned to the high state for at least 10ms to return to the
standby mode. In this mode, the SPIF line remains idle
while monitoring for the next command. This mode
allows the device to minimize current consumption
between commands. Once the device has returned to
standby mode, the bus is automatically reset to accept the
address pulses as the next data block. This safeguard is
intended to reset the bus to a known state (waiting for the
beginning of a write sequence) if the delay exceeds the
reset threshold.
17